Proxy Bits for Low Cost Floating-Point Fused Multiply–Add Unit

Abstract

A new°oating-point fused multiply-add (FMA) unit is proposed in this paper. We observed a group of redundant bits that have no e®ect on the e®ective results of the°oating-point FMA arithmetic, and¯gured out that two proxy bits can replace the redundant bits. We proved the existence of the proxy bits using binary arithmetic keeping track of the negligible bits. Using proxy bits, the proposed FMA unit achieves improvement in terms of cost, power consumption, and performance. The results show that the proposed FMA unit reduces the total area and latency by approximately 17.0% and 32% respectively, compared with a current widely used FMA unit.

FPGA Implementation of Embedded Floating-Point Core with Microarchitectural Support

“…This design modifies the hardware in existing FMA and the impact of CMA is not given. Several authors report the enhancements for FMA in terms of proxy bits for redundant bits [9] and clock gating for low power consumption [10]. Decimal floating point arithmetic [11] is proposed for FMA for the usage of redundant digit-set and 4-bit of two's complement encoding.…”