FPGA Implementation of Embedded Floating-Point Core with Microarchitectural Support

Abstract

Floating point arithmetic is a tedious implementation in General Purpose Processors (GPP) and Application Specific Integrated Circuit (ASIC). ASICs don’t afford the modifications of instruction and algorithms in floating point applications. GPP takes over the floating computations in a separate circuit called a Floating Point Unit (FPU), it makes the FPU consume more power and chip area. This paper presents the FPU which incorporates its hardware circuitry for microarchitectural configuration in FPGA. The proposed FPU provides the RAM blocks for storing the instructions and data alongside floating point arithmetic circuits. Compared to conventional implementation, Fused Multiply-Add (FMA) instruction is implemented with a minimum adder, multiplier, and shifters resources. An instruction stored in RAM selects and controls the floating point operations such as addition, subtraction, multiplication, and Multiply Accumulate (MAC) operations. Pipelined FPU is implemented as a simple microarchitecture in Stratix III FPGA at the maximum operating frequency of 463 MHz; proposed FPU shares some hard floating point circuits in adder multiplier data paths.