Quantitative characterization of the software layer of a HW/SW co-designed processor

Abstract

Abstract-HW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary translation and applies aggressive optimizations through exploiting the runtime application behavior, these hybrid architectures provide better performance/watt. However, a poorly designed software layer can result in significant translation/optimization overheads that may offset its benefits. This work presents a detailed characterization of the software layer of a HW/SW co-designed processor using a variety of benchmark suites. We observe that the performance of the software layer is very sensitive to the characteristics of the emulated application with a variance of more than 50%. We also show that the interaction between the software layer and the emulated application, while sharing the microarchitectural resources, can have 0-20% impact on performance. Finally, we identify some key elements which should be further investigated to reduce the observed variations in performance. The paper provides critical insights to improve the software layer design.

Performance simulation methodologies for hardware/software co-designed processors

“…The TOL overhead varies from almost 0% to 80% (secondary Y-axis). This behavior is expected due to various application characteristics, such as number of indirect branches and the variance in the dynamic / static instruction ratio [59].…”

“…this work, we also wrote technical report [59] about the workload characterization for HW/SW co-designed processors. It includes basic facts about DARCO and characterizes modern benchmarks suites (SPEC2006, Media Bench, Physics Bench).…”

“…The superblock is built when the edges between basic blocks in the superblock are highly biased. Experimentally, it has been shown that the optimal threshold values are: T H BB =5 and T H SB =10000, as it is shown in [59]. Superblocks are created by including basic blocks until the probability to reach the end of the superblock is below 80% based on profiling information.…”

“…The statistics that are used for this work are the statistics that are known from the literature to affect the behavior of the TOL the most. They trigger long operations in terms of host instructions [59] and the ones that are studied are listed as follows:…”