Specifying and verifying systems with multiple clocks

Clarke, Edmund M.; Kroening, Daniel; Yorav, Karen

doi:10.1109/iccd.2003.1240872

Cited by 8 publications

(9 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, if the clocks are generated from independent sources, they are in general unsynchronized, typically with fixed frequencies but unknown initial phases. For modeling such systems, we consider one representative at a time from the various combination scenarios of initial phases, unlike the work of Clarke et al [18] where all possible scenarios are considered simultaneously in modeling. Our goal is to trade generality for scalability of the BMC methods.…”

Section: A Clocked Ltl Specificationsmentioning

confidence: 98%

“…Note that these approaches focus mainly on reducing the number of flip-flops in order to improve the scalability of BDD-based model checking, and not so much on reducing the number of logic gates. In another approach by Clarke et al [18], given multiple clock frequency constraints, a clock state machine is built based on event queue semantics. Each clock state maps to a configuration (i.e., a 3C-2 set of events) in an event queue where each event corresponds to a tick of an active clock.…”

Section: B Related Workmentioning

confidence: 99%

“…Previously proposed solutions have been largely piece-wise, such as translating clocked LTL properties [13] that can be handled by a standard BMC solver, reducing the verification model size by using phase abstraction techniques [14][15][16][17], and generating a clocking scheme from given frequency constraints based on event queue semantics to avoid unnecessary unrolling during BMC [18].…”

Section: A Motivationmentioning

confidence: 99%

See 2 more Smart Citations

Efficient BMC for Multi-Clock Systems with Clocked Specifications

Ganai

Gupta

2007

2007 Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

Current industry trends in system design -multiple clocks, clocks with arbitrary frequency ratios, multi-phased clocks, gated clocks, and level-sensitive latches, combined with clocked -pose additional challenges to verification efforts. We propose an integrated solution that improves SAT-based Bounded Model Checking (BMC) by orders of magnitude, for verification of synchronous multi-clock systems with clocked LTL properties. Our main contributions are: a) Efficient clock modeling schemes to handle clock related challenges uniformly, b) Generation of automatic schedules and clock constraints to avoid unnecessary unrolling and loop-checks in BMC, c) Dynamic simplification of BMC problem instances with clock constraints, and d) Customized BMC translations-with incremental formulations and learning-to directly handle PSL-style clocked specifications. We demonstrate the effectiveness of our approach on some OpenCores multi-clock system benchmarks. I IntroductionA continuing push for high performance and low power designs has greatly increased the system design complexity. One norm of today's System-on-Chip (SoC) design is the use of multiple clocks and phases, and gated clocks. This paradigm shift from a single global clock synchronous design paradigm was inevitable, as distributing a single clock across the increasing size of die, number of latches, frequencies of clocks and delays of wires poses a major bottleneck in achieving the goals of higher performance and lower power [1]. For power-conscious designs, designers often use gated clocks to reduce or disable the switching activity of certain portions of the design. Furthermore, SoC designs comprise several intellectual property (IP) blocks that operate at different clock frequencies and need to communicate across asynchronous clock domains. Each of these design styles increases the verification complexity in terms of increased number of state bits and deeper bug traces.Formal verification techniques like SAT-based Bounded Model Checking (BMC) [2-5] due to several advancements -improved DPLL-style SAT solvers [6], on-the-fly circuit simplification [7,8], partitioning and incremental BMC formulation [9], and SAT-based incremental learning [8, 10, 11] -have been gaining wide acceptance as a scalable solution compared to BDD-based symbolic model checking [12]. The performance of SAT-based BMC is less sensitive to the number of flip-flops (FFs) and does not suffer from space explosion. A. MotivationAn integrated solution to verify multi-clock systems comprising multiple clocks, clocks with arbitrary frequency ratios, multi-phased clocks, gated clocks, level-sensitive latches, combined with clocked specification, that exploits recent advancements in SAT-based BMC has been lacking. Previously proposed solutions have been largely piece-wise, such as translating clocked LTL properties [13] that can be handled by a standard BMC solver, reducing the verification model size by using phase abstraction techniques [14][15][16][17], and generating a clocking scheme from given fr...

show abstract

Section: A Clocked Ltl Specificationsmentioning

confidence: 98%

Section: B Related Workmentioning

confidence: 99%

Section: A Motivationmentioning

confidence: 99%

See 1 more Smart Citation

Efficient BMC for Multi-Clock Systems with Clocked Specifications

Ganai

Gupta

2007

2007 Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…In [6], the authors present a methodology for modelling the relations between clock domains, such that designs can be verified under any formal technique. This is done by translating clock constraints into state machines representing these relations.…”

Section: B Prior Workmentioning

confidence: 99%

Multiple clock domain synchronization in a QBF-based verification environment

Maksimovic

Veneris

2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

Abstract-Modern designs are growing in size and complexity, becoming increasingly harder to verify. Today, they are architected to include multiple clock domains as a measure to reduce power consumption. Verifying them proves to be a computationally intensive and challenging task as it requires their clocks to be synchronized. To achieve synchronization, existing Boolean satisfiability-based methodologies add hardware to combine the clock domains before transforming them into their iterative logic array representation (ILA). As a consequence, this results in the addition of redundant time-frames adding overhead during verification. This paper introduces a novel framework to verify designs with multiple clocks using Quantified Boolean Formula satisfiability (QBF). We first present a formulation that models an ILA representation with symbolic universal quantification to achieve synchronization. This is later extended with the use of a clock divider to overcome inefficiencies. The net effect is the reduction in the number of redundant time-frames. Furthermore, the usage of QBF results in significant memory savings when compared to traditional methods. Experiments on bounded model checking demonstrate memory reductions of 76% on average with competitive run-time performance.

show abstract

“…A specification describes the correct timing behavior of a design. The work in [6] presents a formal method to specify the relations between multiple clocks and to model the possible behaviors. Then, a hardware design is verified against the specified clock constraints.…”

mentioning

confidence: 99%

Debug Automation for Synchronization Bugs at RTL

Dehbashi

Fey

2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

View full text Add to dashboard Cite

Abstract-One major concern in the design of Very-LargeScale Integrated (VLSI) circuits is debugging as design size and complexity increase. Automation of the debugging process helps to decrease the development cycle of VLSI circuits and consequently to achieve a higher productivity. This paper presents an approach to automatically debug synchronization bugs due to coding mistakes at RTL. In particular, we introduce an appropriate bug model and show how synchronization bugs are differentiated from other types of bugs by our approach. The experimental results on LGsynth93 and ITC-99 benchmark suites and RTL modules of OpenRISC and OpenSPARC CPUs show diagnosis accuracy and efficiency of the approach.Keywords-debug automation, synchronization bug, SAT-based debugging I. INTRODUCTION Due to the increasing design size and complexity of VLSI circuits, the cost of VLSI systems verification and debugging has significantly increased. Verification tools check the correctness of a design against its specification. Upon detection of a design error, the error is returned as a counterexample. Having a counterexample, the debug process starts localizing and rectifying the bug. But this process is often a manual task which needs a large effort. Thus, automated approaches to design debugging are necessary to decrease the development cycle of VLSI products.Design bugs at RTL are classified into three major classes: logic bugs, algorithmic bugs and synchronization bugs . Algorithmic bugs can have a severe impact on the correctness of a design and they usually require multiple major modifications to be fixed. Synchronization bugs are related to synchronization of data with respect to clock cycles in a design. For most of the synchronization bugs, a signal requires to be latched a cycle earlier or a cycle later in order to keep the correct timing behavior of signals in the design [1]. The most common fix for this class of design bugs is the manual addition or removal of flipflops to satisfy the correct timing behavior of the circuit. These bug models are called missing flipflop and extra flipflop.In the pre-silicon stage, a design is verified against its specification by verification tools. A specification describes the correct timing behavior of a design. The work in [6] presents a formal method to specify the relations between multiple clocks and to model the possible behaviors. Then, a hardware design is verified against the specified clock constraints. An efficient clock modeling approach is presented in [7] to handle clock related challenges uniformly. The approach converts multiple clocks with arbitrary frequencies and ratios, gated clocks, multiple phases, latches and flip-flops in multi-clock synchronous system, into a single-clock model. Clock constraints are automatically generated to avoid unnecessary unrolling and loop-checks in Bounded Model Checking (BMC).The work in [2] presents a model based on Boolean satisfiability to automate debugging of logic bugs. A circuit is enhanced with correction block in order to find the...

show abstract

Specifying and verifying systems with multiple clocks

Cited by 8 publications

References 11 publications

Efficient BMC for Multi-Clock Systems with Clocked Specifications

Efficient BMC for Multi-Clock Systems with Clocked Specifications

Multiple clock domain synchronization in a QBF-based verification environment

Debug Automation for Synchronization Bugs at RTL

Contact Info

Product

Resources

About