Spec-based repeater insertion and wire sizing for on-chip interconnect

Menezes, Noel; Chen, Chung-Ping

doi:10.1109/icvd.1999.745201

“…A detailed description of handling transition-time effects is given in [9]. We assert here that a repeater insertion algorithm will suffer from significant accuracy problems if transition-time effects are not taken into account.…”

Section: Transition-time Effectsmentioning

confidence: 98%

“…(We omit an algorithm description for brevity. For this, we direct the interested reader to [3,4,9].) For an RC network as shown in Figure 1, the algorithms of [3,4] starts at the receivers, SR i , and inserts repeaters from the set of allowable repeaters B in turn at the end point of each routing segment e i of the tree.…”

Section: The Ginneken/lillis Algorithmmentioning

confidence: 99%

“…• An accurate repeater/driver model [12,13] that takes resistance-shielding of the RC net is into account in addition to providing accurate waveform estimates at the sinks is used. The techniques presented here have been partially presented elsewhere [9] but we describe them again for completeness. To the best of our knowledge this is the first work in interconnect optimization that handles delay, transition-time, and noise constraints in a single framework by the use of advanced delay models for both the linear RC as well as the driver/repeater components of on-chip nets.…”

Section: Introductionmentioning

confidence: 98%

See 1 more Smart Citation

Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching

Chen

¹

,

Menezes

²

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] a noiseaware repeater insertion technique has also been proposed recently. Recognizing the conservatism of these delay and noise models, we propose a moment-matching based technique to interconnect optimization that allows for much higher accuracy while preserving the hierarchical nature of Elmore-delay-based techniques. We also present a novel approach to noise computation that accurately captures the effect of several attackers in linear time with respect to the number of attackers and wire segments. Our practical experiments with industrial nets indicate that the corresponding reduction in error afforded by these more accurate models justifies this increase in runtime for aggressive designs which is our targeted domain. Our algorithm yields delay and noise estimates within 5% of circuit simulation results.

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“…Several circuit models have been proposed to compute the delay or power dissipation of repeaters such as the switch-level RC model [7], the generalized model considering slew rate [13], and the moment matching model [2,15]. Various design objectives are used such as delay minimization [3,11,17], power minimization [9,12,16], and cross-coupling noise reduction [1,5].…”

Section: Previous Researchmentioning

confidence: 99%

Low-power repeater insertion with both delay and slew rate constraints

Peng

¹

,

Liu

²

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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In this paper, a novel repeater insertion algorithm is presented to minimize the power dissipation of interconnect trees under given timing budgets and slew rate constraints. In contrast to traditional bottom-up dynamic programming approaches, the proposed algorithm combines a Lagrangian relaxation framework and a graphbased search method to derive possible solutions in a top-down fashion. As a result, it is capable of analyzing repeater slew rates efficiently. In addition, our scheme incorporates accurate circuit models and is therefore able to capture the precise delay and slew rate information, leading to high-quality interconnect designs.We have applied our scheme to interconnects of different topologies and various timing and slew rate constraints. Experimental results demonstrate the effectiveness of our approach in comparison with previous low-power repeater insertion schemes. Under tight timing constraints, our scheme can always derive repeater insertion solutions that meet both delay and slew rate requirements, whereas other schemes often fail. Under loose timing constraints, our algorithm achieves up to a 23% average power dissipation reduction for different interconnects specifications with shorter runtimes.

show abstract

“…Several circuit models have been proposed to compute the delay or power dissipation of repeaters such as the switch-level RC model [7], the generalized model considering slew rate [13], and the moment matching model [2,15]. Various design objectives are used such as delay minimization [3,11,17], power minimization [9,12,16], and cross-coupling noise reduction [1,5].…”

Section: Previous Researchmentioning

confidence: 99%

Low-power repeater insertion with both delay and slew rate constraints

Peng

¹

,

Liu

²

2006

2006 43rd ACM/IEEE Design Automation Conference

1

0

View full text Add to dashboard Cite

In this paper, a novel repeater insertion algorithm is presented to minimize the power dissipation of interconnect trees under given timing budgets and slew rate constraints. In contrast to traditional bottom-up dynamic programming approaches, the proposed algorithm combines a Lagrangian relaxation framework and a graphbased search method to derive possible solutions in a top-down fashion. As a result, it is capable of analyzing repeater slew rates efficiently. In addition, our scheme incorporates accurate circuit models and is therefore able to capture the precise delay and slew rate information, leading to high-quality interconnect designs.We have applied our scheme to interconnects of different topologies and various timing and slew rate constraints. Experimental results demonstrate the effectiveness of our approach in comparison with previous low-power repeater insertion schemes. Under tight timing constraints, our scheme can always derive repeater insertion solutions that meet both delay and slew rate requirements, whereas other schemes often fail. Under loose timing constraints, our algorithm achieves up to a 23% average power dissipation reduction for different interconnects specifications with shorter runtimes.

show abstract

Spec-based repeater insertion and wire sizing for on-chip interconnect

Cited by 15 publications

References 20 publications

Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching

Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching

Low-power repeater insertion with both delay and slew rate constraints

Low-power repeater insertion with both delay and slew rate constraints

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