Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching

Abstract

Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] a noiseaware repeater insertion technique has also been proposed recently. Recognizing the conservatism of these delay and noise models, we propose a moment-matching based technique to interconnect optimization that allows for much higher accuracy while preserving the hierarchical nature of Elmore-delay-based techniques. We also present a novel approach to noise computation that accurately captures the effect of several attackers in linear time with respect to the number of attackers and wire segments. Our practical experiments with industrial nets indicate that the corresponding reduction in error afforded by these more accurate models justifies this increase in runtime for aggressive designs which is our targeted domain. Our algorithm yields delay and noise estimates within 5% of circuit simulation results.

Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method

“…Several circuit models have been proposed to compute the delay or power dissipation of repeaters such as the switch-level RC model [9], the generalized model considering slew rate [14], and the moment matching model [3]. Various design objectives are used such as delay minimization [4,12,19], power minimization [6,10,13,16,18], and cross-coupling noise reduction [1,7].…”

Post-route gate sizing for crosstalk noise reduction

“…Noise can be reduced through routing and interconnect optimization (wire spacing, wire widening, controlling coupling length and position) [10,11], buffer insertion [12,13] and driver sizing. In the post-route design stage, it is not desirable to use techniques such as wire perturbations and buffer insertion since they would require re-routing and thus increase design time.…”

Crosstalk noise optimization by post-layout transistor sizing

“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Buffer insertion is also effective for noise reduction, and some methods are proposed [4,5]. References [6][7][8] discuss the effectiveness of transistor sizing for crosstalk noise reduction, but practical implementations are not shown.…”