Crosstalk noise optimization by post-layout transistor sizing

Abstract

This paper proposes a post-layout transistor sizing method for crosstalk noise reduction. The proposed method downsizes the drivers of the aggressor wires for noise reduction, utilizing the precise interconnect information extracted from the detail-routed layouts. We develop a transistor sizing algorithm for crosstalk noise reduction under delay constraints, and construct a crosstalk noise optimization method utilizing a crosstalk noise estimation method and a transistor sizing framework which are previously developed. Our method exploits the transistor sizing framework that can vary the transistor widths inside cells with interconnects unchanged. Our optimization method therefore never cause a new crosstalk noise problem, and does not need iterative layout optimization. The effectiveness of the proposed method is experimentally examined using 2 circuits. The maximum noise voltage is reduced by more than 50% without delay increase. These results show that the risk of crosstalk noise problems can be considerably reduced after detailrouting.

Technology mapping with crosstalk noise avoidance

“…Generally, at the postrouting stage, crosstalk reduction can be achieved by transistor sizing, gate sizing or wire sizing for the accurate noise analysis based on the RC extraction of layout [24], [4], [8], [9], [23]. However, the flexibility of adjusting netlists might not be enough to fix hundreds or even thousands of interconnect noise problems, so eventually those unsolved noise problems would only rely on the rip-up and reroute step.…”

Reliable crosstalk-driven interconnect optimization

“…The coupling information can be completely extracted after detailed routing. The typical techniques to reduce the coupling capacitance include buffer insertion [Alpert et al 1998;Zhang and Sapatnekar 2004], wire permutation [Gao and Liu 1993], wire perturbation [Saxena and Liu 1999], wire shielding [Rabaey 1996], wire sizing [Jiang et al 2000], and gate sizing [Hashimoto et al 2002;Becer et al 2003;Jiang et al 2000;. Since wire and gate sizing can be done by incremental changes, they are suitable for post-layout optimization.…”