Space radiation and reliability qualifications on 65nm CMOS 600MHz microprocessors

Clerc, Sylvain; Abouzeid, Fady; Gasiot, Gilles; Daveau, Jean-Marc; Bottoni, Cyril; Glorieux, Maximilien; Autran, J.L.; Cacho, F.; Huard, V.; Dugoujon, L.; Weigand, Roland; Malou, Florence; Hili, Laurent; Roché, Philippe

doi:10.1109/irps.2013.6532051

Cited by 7 publications

(2 citation statements)

References 8 publications

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“…An example of an ASIC prototype based on commercial technology was the AT697E, an ASIC prototype of the LEON2FT from Atmel based on a 180 nm CMOS process. b) RHBD technologies: In Europe many ASICs are based on the RHBD DARE library for the UMC 180 nm CMOS technology [97] and the newer C65SPACE (65 nm) by STMicroelectronics [98]. The AT697F was based on the ATC18RHA (180nm) rad-hard library, providing an increase in resilience to TID effects from 60 to 300 krad compared with the AT697E.…”

Section: Hardware Modelsmentioning

confidence: 99%

Leveraging the Openness and Modularity of RISC-V in Space

Mascio¹,

Menicucci²,

Gill³

et al. 2019

Journal of Aerospace Information Systems

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This paper proposes a roadmap to address present and future needs in space systems with RISC-V processors. RISC-V is an open and modular instruction set architecture, which is rapidly growing in popularity in terrestrial applications. To satisfy different applications with contrasting requirements in satellite data systems, four different types of processors are identified: 1) low-area/low-power microcontrollers, 2) on-board computers, 3) general-purpose processors for payloads, and 4) enhanced payload processors for artificial intelligence. Several solutions based on RISC-V are proposed for each of these types of processors and compared with proprietary commercial-off-the-shelf and spacegrade solutions. An extensive analysis of the results available from literature is conducted to show that RISC-V has the potential to solve such a wide range of needs. This paper will also show the unprecedented number of open-source implementations and models that were developed in a relative short time on a single instruction set architecture. Future space systems could benefit from many of those developments, and this work identifies and highlights what is still missing to satisfy the specific needs of processors for space, especially in terms of fault tolerance and technology readiness level.

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Section: Hardware Modelsmentioning

confidence: 99%

Leveraging the Openness and Modularity of RISC-V in Space

Mascio¹,

Menicucci²,

Gill³

et al. 2019

Journal of Aerospace Information Systems

View full text Add to dashboard Cite

show abstract

“…The first one is fully mapped (i.e gate and flip-flops) on standard unhardened cells while the second one is implemented with hardenedby-design flip-flops and clock tree cells [6]. It is important to note that hardened-by-design combinational cells were not used for any implementation due to their area overhead.…”

Section: Device Under Testmentioning

confidence: 99%