2017 IEEE International Electron Devices Meeting (IEDM) 2017
DOI: 10.1109/iedm.2017.8268518
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Solving the BEOL compatibility challenge of top-pinned magnetic tunnel junction stacks

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Cited by 20 publications
(7 citation statements)
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“…3b. With the assistance of SOT, Jth-STT as low as 0.94 MA•cm -2 can be achieved, which is a remarkable decrease compared to other current-induced mechanisms, 35,37,49 hence the ultralow power switching is expected. 48 Moreover, the reduction of charge current passing through the MgO barrier can benefit the lifetime of p-MTJ devices.…”
Section: Three-terminal Sot and Stt Devicesmentioning
confidence: 98%
“…3b. With the assistance of SOT, Jth-STT as low as 0.94 MA•cm -2 can be achieved, which is a remarkable decrease compared to other current-induced mechanisms, 35,37,49 hence the ultralow power switching is expected. 48 Moreover, the reduction of charge current passing through the MgO barrier can benefit the lifetime of p-MTJ devices.…”
Section: Three-terminal Sot and Stt Devicesmentioning
confidence: 98%
“…We note that this approach is not straightforward for SOT, as MgO would be inserted in between the SOT and FL layers, resulting in degradation of spin current transfer. As an alternative, the concept of a hybrid FL, i.e., a FL composed of a reading CoFeB-based layer coupled to a magnetic layer or multilayer with stronger PMA [190,191] was recently demonstrated [132,192,193]. This solution significantly improves the thermal stability factor to Δ > 100 in 50 nm pillars [Fig.…”
Section: Free Layermentioning
confidence: 99%
“…In fact, the atomic intermixing at interfaces and strain induced by the growth of differently textured materials lead to an overall device performance deterioration, for example, FL and SAF loss of PMA (and Ms). Whereas in-plane MTJs were readily BEOL-compatible owing to the thicker FM layer, perpendicularly magnetized MTJ stacks reached 400 °C compatibility only two years ago [190,227], and SOT-MTJ stacks were recently demonstrated [132,154]. A challenge that can significantly impact the yield is that the etching of the MTJ has to stop on the thin SOT channel precisely (typically less than 5 nm thick) without degrading its conductivity or causing vertical shorts due to metal re-deposition on the tunnel barrier sidewalls.…”
Section: Sot-mtj Integration and Challengesmentioning
confidence: 99%
“…In order to integrate STT-MRAM with the CMOS fabrication process, MTJs must sustain at least 400C temperature typical for the back-end-of-line process. Recently, IMEC reported a process allowing to preserve the high TMR and thermal stability of MTJs [43]. The idea is to invert the free and the fixed layer by putting the fixed layer on top of the MTJ.…”
Section: Spin-transfer Torque Mrammentioning
confidence: 99%