SOI/SOI/Bulk-Si triple-level structure for three-dimensional devices

Abstract

The fabrication procedure of the SOI/SOI/bulk-Si triplelevel structure is developed by using the improved selective laser recrystallization technique and MOS LSI technology. The enlarged crystal stripes sandwiched by straight grain boundaries are produced on the planarized insulating film which overlies the device structure in bulkSi, and also SOUbulk-Si double-layered structure. The basic characteristics of MOSFET's in a triple-level structure are evaluated.

Clock Distribution Networks in 3-D Integrated Systems

“…6, where some salient features of this technology are also depicted. SOI technologies are particularly suitable for 3-D circuits, since the SOI device layers can be used for both monolithic [22] and wafer level 3-D integrated systems. In the latter case, SOI is a better solution for 3-D circuits because it is possible to aggressively etch the wafers as compared to standard bulk CMOS technologies [23].…”

Clock distribution architectures for 3-D SOI integrated circuits

“…SOI technologies are particularly suitable for 3-D circuits, since the SOI device layers can be used for both monolithic [5] and wafer level 3-D integrated systems. In the latter case, SOI constitutes a better solution for 3-D circuits due to the capability to more aggressively etch the wafers as compared to standard CMOS technologies.…”

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

“…In addition, the growth of the devices on the upper planes usually requires high temperatures. Insulator layers are used to protect the transistors on the first plane [40]. These insulators, however, further encumber the heat removal process with negative consequences for a monolithic 3-D circuit.…”

“…Monolithic 3-D ICs include layers of planar devices successively grown on a conventional complementary metal-oxide-semiconductor (CMOS) or SOI plane [40]. Monolithic 3-D circuits support transistor-level integration.…”