Clock Distribution Networks in 3-D Integrated Systems

Pavlidis, Vasilis F.; Savidis, Ioannis; Friedman, Eby G.

doi:10.1109/tvlsi.2010.2073724

Cited by 39 publications

(13 citation statements)

References 23 publications

(38 reference statements)

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“…Fig. 1 (a) shows a basic tree method for connecting between chips that are in a vertical straight line [3][4][5][6][7]. The structure in Fig.…”

Section: Related Workmentioning

confidence: 99%

“…Several researchers have developed effective methods for the clock distribution network (CDN) of 3D ICs [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] such as 3D clock tree synthesis. Several techniques have been proposed for CDN physical structures.…”

Section: Introductionmentioning

confidence: 99%

“…Several techniques have been proposed for CDN physical structures. The most basic structure is a 2D clock tree with a single TSV between adjacent chips as shown in [2][3][4][5][6][7]. The structure of a 3D clock tree using multiple TSVs can be seen in [2,3,8].…”

Section: Introductionmentioning

confidence: 99%

“…The structure of a 3D clock tree using multiple TSVs can be seen in [2,3,8]. Pavlidis et al [4] have proposed an Htree with local and/or global rings. Kim et al have proposed a method linking among the stacked H-tree sinks which is called a distributed multi-TSV 3D CDN (DMT 3D CDN) [5], and a method that tapered the number of TSVs which is called a vertical tree 3D CDN (VT 3D CDN) [6].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Clock skew reduction for stacked chips using multiple source buffers

Niioka

Imai

Fukase

et al. 2015

2015 15th International Symposium on Communications and Information Technologies (ISCIT)

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In this paper, we propose a method to reduce clock skew among stacked chips by a clock distribution network with multiple source buffers (MSB CDN). The propagation delays to all chips that need a clock signal are tuned only in the chip with a clock source. The adjustment is done in accordance with the size and number of buffers. Receivers in the same conditions are placed on the other chips. The output signals of the receivers are subjected to waveform shaping. In this way, the delays and slews are unified. The proposed method has the advantage that all the chips except for the chip with a clock source can be designed by using a conventional method such as buffered clock tree synthesis (CTS). The experimental results demonstrate that the proposed method can reduce clock skew.

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“…Fig. 1 (a) shows a basic tree method for connecting between chips that are in a vertical straight line [3][4][5][6][7]. The structure in Fig.…”

Section: Related Workmentioning

confidence: 99%