A Fractal Ultra-High-Speed Oscillator/Distributor Network with Structural Robustness to Voltage and Temperature Gradients

Abstract

Abstract

Ring-Oscillator Type Multi-Chip Clock Signal Synchronization Technique with In-Phase Clock Bus Lines

“…The technique suggested in this paper can minimize the clock skews between clock signals generated under asymmetrical voltage condition in a very simpler way than the existing PLL method above mentioned [6]. Moreover, it allows us to reduce layout design area in current well-developed CMOS technology.…”