Abstract. GHz level ultra high speed clock generation and distribution for synchronization becomes a very important technical issue in chip and SoC applications. This paper proposes a novel way of CMOS GHz cellular oscillator/distributor networks with inherent insensitivities to supply-voltage and temperature fluctuations. Simulation results prove that maximun clock skew is limited within ~1% of a system clock period, given 3% of power supply and/or 5% of temperature fluctuations. This technique can thus be used for a low skew clock distribution in a few GHz speed VLSI and SoC systems design.The SPICE simulations are carried out with 3V, 0.5μm CMOS N-well process parameters to prove the novelity as well as the validity of the idea. Layout is also included for the future chip fabrication.

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A new version of the well-known FSK (Frequency-Shift Keying) modulation technique for telecommunication system was proposed and verified. A simple form of ring oscillator with three inverters was adopted for the basic frequency generator. The frequency shift was realized using a ring oscillator composed of nine inverters. CMOS multiplexers were used to select one of two different oscillators, i.e., to shift between two different frequencies. Simulations were performed for the verification.

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