Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Pavlidis, Vasilis F.; Friedman, Eby G.

doi:10.1109/jproc.2008.2007473

Cited by 110 publications

(32 citation statements)

References 105 publications

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“…This behavior is because the horizontal area (i.e., wire length) occupied by each tree in scheme A is the greatest among the four schemes, requiring the largest number of buffers. As described by (1) and (3), the skew variations of scheme A are higher than the other schemes.…”

Section: A Uncorrelated Wid Variationsmentioning

confidence: 90%

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Skew variability in 3-D ICs with multiple clock domains

Pavlidis

Micheli

2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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Abstract-The effect of process variations on the clock skew in three dimensional (3-D) circuits with multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra-die process variations should be considered in the design of clock distribution networks. A statistical clock skew model incorporating spatially correlated intra-die process variations is employed to describe this effect. The clock skew is shown to change in different ways with the allocation of the clock domains within the 3-D circuit. Various schemes to assign the clock domains are investigated. Different scenarios of inter-die and intra-die process variations and an intra-die spatial correlation model are applied to these schemes. An approach where each physical plane corresponds to a single clock domain is shown to be inferior to other clocking schemes for specific variation scenarios. Tradeoffs between the number of clock domains within a physical plane and the number of planes a clock tree spans are discussed and related design guidelines are offered.

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Section: A Uncorrelated Wid Variationsmentioning

confidence: 90%

“…3-D integration emerges as a potent solution to alleviate the increasing interconnect delay in modern ICs [1]. Considering the important synchronization issue, the reduced interconnect latency can be exploited to either relax the clock skew constraints or further increase the speed of a circuit.…”

Section: Introductionmentioning

confidence: 99%

Skew variability in 3-D ICs with multiple clock domains

Pavlidis

Micheli

2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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“…Three-dimensional integration demonstrates many opportunities for heterogeneous SoCs [9]. Integrating circuits from diverse fabrication processes into a single multiplane system can result in substantially different interconnect impedance characteristics of each physical plane within a 3-D circuit.…”

Section: Timing Optimization Of Interplane Interconnectsmentioning

confidence: 99%

“…This heterogeneity, however, greatly complicates the interconnect design process within a multi-plane system, as potential design methodologies need to manage the diverse interconnect impedance characteristics and process variations caused by the different fabrication processes and technologies employed in the multiple physical planes [9]. Additional primary challenges in 3-D circuits include the development of methodologies at the front end of the design process [10], [11], multi-plane functional testing [12], thermal management techniques [13], and maturing manufacturing technologies [14].…”

Section: Introductionmentioning

confidence: 99%

Physical Design Issues in 3-D Integrated Technologies

Pavlidis¹,

Friedman

2010

IFIP Advances in Information and Communication Technology

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Abstract. Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.

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“…Three-dimensional (3D) integrated circuits (ICs) with through-silicon vias (TSVs) were introduced to overcome the well-known wall problems of two-dimensional (2D) ICs, such as interconnect problems [1], [2]. Memory plays an important role in high performance systems and will likely be the first commercial application of 3D IC technology [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Yield Enhancement Techniques for 3D Memories by Redundancy Sharing among All Layers

Lee¹,

Park²,

Kang³

2012

ETRI J

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Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multilayer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

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Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Abstract: Several interesting research problems in the design of 3-D circuits are also discussed.

Cited by 110 publications

References 105 publications

Skew variability in 3-D ICs with multiple clock domains

Skew variability in 3-D ICs with multiple clock domains

Physical Design Issues in 3-D Integrated Technologies

Yield Enhancement Techniques for 3D Memories by Redundancy Sharing among All Layers

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