Clock distribution architectures for 3-D SOI integrated circuits

Pavlidis, Vasilis F.; Savidis, Ioannis; Friedman, Eby G.

doi:10.1109/soi.2008.4656319

Cited by 6 publications

(4 citation statements)

References 8 publications

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“…Experiments . demonstrate that a clock distribution network that combines an H-tree on the second plane and meshes on the other two planes exhibits moderate skew, within 10% of the clock period, and the lowest power consumption [57], [58]. The superior performance of this topology is due to the symmetry of the H-tree and the balancing characteristic of the meshes.…”

Section: Synchronization In 3-d Circuitsmentioning

confidence: 90%

Physical Design Issues in 3-D Integrated Technologies

Pavlidis¹,

Friedman

2010

IFIP Advances in Information and Communication Technology

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Abstract. Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.

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Section: Synchronization In 3-d Circuitsmentioning

confidence: 90%

Physical Design Issues in 3-D Integrated Technologies

Pavlidis¹,

Friedman

2010

IFIP Advances in Information and Communication Technology

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“…Different clock network topologies can be considered to adapt the conventional (planar) resonant clock networks to 3-D circuits [2]. In the first topology denoted as "symmetric topology", each plane contains resonant circuits and can be separately investigated.…”

Section: Resonant Clocking For 3-d Icsmentioning

confidence: 99%

“…Aprimary challenge in designing synchronous circuits is how to distribute the clock signal to the sequential parts of the circuit [1].This issue can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics [2].…”

Section: Introductionmentioning

confidence: 99%

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits

Rahimian

Pavlidis

Micheli

2011

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

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Abstract. Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing clock signal to the sink nodes. A design method for 3-D resonant clock networks is presented. The proposed design technique supports resonant operation for pre-bond test, an important requirement for 3-D ICs. Several 3-D clock network topologies are explored in a 0.18 μm CMOS technology. Simulation results indicate 43% reduction in the power consumed by the resonant 3-D clock network as compared to a conventional buffered clock network.

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“…This issue can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics [2].…”

Section: Introductionmentioning

confidence: 99%

Low-power clock distribution networks for 3-D ICs

Rahimian

Micheli

Pavlidis

2012

2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel

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Abstract-Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing clock signal to the sink nodes. Test is another complex task for 3-D ICs, where pre-bond test is a prerequisite. This paper, consequently, introduces a design methodology for resonant 3-D clock networks that lowers the power of the clock networks while supporting pre-bond test.

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Clock distribution architectures for 3-D SOI integrated circuits

Cited by 6 publications

References 8 publications

Physical Design Issues in 3-D Integrated Technologies

Physical Design Issues in 3-D Integrated Technologies

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits

Low-power clock distribution networks for 3-D ICs

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