Abstract. Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing clock signal to the sink nodes. A design method for 3-D resonant clock networks is presented. The proposed design technique supports resonant operation for pre-bond test, an important requirement for 3-D ICs. Several 3-D clock network topologies are explored in a 0.18 μm CMOS technology. Simulation results indicate 43% reduction in the power consumed by the resonant 3-D clock network as compared to a conventional buffered clock network.
Three-dimensional (3-D) integration is an emerging candidate for implementing high performance multifunctional systems-on-chip. Employing an efficient medium for data communication among different planes is a key factor in achieving a high performance 3-D system. Through Silicon Vias (TSVs) provide high bandwidth, high density inter-plane links while facilitating the flow of heat in 3-D circuits. This paper provides an overview of the diverse applications of TSVs within 3-D circuits and surveys the manufacturing and design challenges relating to these interconnects. Inter-plane communication through AC-coupled on-chip inductors is also discussed as an alternative to TSVs. Although there have been several efforts that model the electrical characteristics of these inter-plane communication schemes, the effect that heat can have on the performance of the inter-plane link implemented with either means has not sufficiently been investigated. Consequently, some insight on the effects of thermal gradients on the performance of these links is offered. Results indicate that the electrical performance of TSV is not susceptible to temperature variations. Signal integrity can, however, be degraded in the case of pronounced thermal gradients in contactless 3-D ICs, as demonstrated by a decay of the S-parameters for the investigated inductive links.
Abstract-Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing clock signal to the sink nodes. Test is another complex task for 3-D ICs, where pre-bond test is a prerequisite. This paper, consequently, introduces a design methodology for resonant 3-D clock networks that lowers the power of the clock networks while supporting pre-bond test.
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