2009 IEEE International SOI Conference 2009
DOI: 10.1109/soi.2009.5318737
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SOI gated resistor: CMOS without junctions

Abstract: We report the fabrication of junctionless SOI MOSFETs. Such devices greatly simplify processing thermal budget and behave as regular multigate SOI transistors.

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Cited by 130 publications
(80 citation statements)
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“…4 Recently, a nanowire transistor called the "junctionless transistor" or the "gated resistor" has been introduced. 5,6 It is made of an N + ͑or P + for a p-channel device͒ doped silicon nanowire with a gate electrode. The doping concentration typically ranges between 10 19 and 8 ϫ 10 19 cm −3 .…”
Section: Reduced Electric Field In Junctionless Transistorsmentioning
confidence: 99%
See 1 more Smart Citation
“…4 Recently, a nanowire transistor called the "junctionless transistor" or the "gated resistor" has been introduced. 5,6 It is made of an N + ͑or P + for a p-channel device͒ doped silicon nanowire with a gate electrode. The doping concentration typically ranges between 10 19 and 8 ϫ 10 19 cm −3 .…”
Section: Reduced Electric Field In Junctionless Transistorsmentioning
confidence: 99%
“…Using a trigate device architecture it is possible to turn the device on and off and to obtain MOSFET-like electrical characteristics. 5,6 Even though the electrical characteristics of the junctionless transistor are similar to those of a regular MOSFET, there is a fundamental difference between the two devices. Classical MOSFETs, including multigate field-effect transistor, are normally-off devices, as the drain junction is reverse biased and blocks current flow if no channel is created between source and drain.…”
Section: Reduced Electric Field In Junctionless Transistorsmentioning
confidence: 99%
“…The device is a multigate silicon nanowire ͑or nanoribbon͒ with a pi-gate ͑multigate͒ architecture and a uniform, heavy doping concentration across the device. 7,8 The fabricated devices reported here have a width ranging from 20 to 50 nm, a thickness ranging from 5 to 10 nm and a gate length of 1 m. The gate oxide thickness is 10 nm and the buried oxide thickness is 340 nm. The junctionless transistors are n-channel devices with a unoform n-type doping concentration of 10 19 cm −3 in the source, drain and channel region.…”
mentioning
confidence: 99%
“…1) has been proposed [12,13]. The JNT is basically a uniformly doped stripe of silicon from source to drain terminals, surrounded by the gate stack, working as a multiple gated resistor [14]. The junctionless transistors seem to be an interesting proposal for the ultimate technological nodes, once it has shown many advantages over IM transistors for both analog and digital applications [15][16][17].…”
Section: Introductionmentioning
confidence: 99%