SMApproxLib: Library of FPGA-based Approximate Multipliers

Ullah, Salim; Murthy, Sanjeev Sripadraj; Kumar, Akash

doi:10.1109/dac.2018.8465845

Cited by 46 publications

(31 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this part, we have confined the approximate operation to the approximate multiplication with XMUL and executed addition and subtraction on the Exact Part with ADD and SUB instructions. Two 16 × 16 bits approximate multipliers, ApM1 and ApM2, are chosen in SMApproxLib [45] which is an open-source approximate multiplier library designed for FPGAs by considering the LUT structure and carry chains of modern FPGAs. Approximation level of our multiplier is again 2 for 8-bit dataset, 3 for 16-bit dataset.…”

Section: Exact Addition/subtraction and Approximate Multiplicationmentioning

confidence: 99%

Approximate CPU Design for IoT End-Devices with Learning Capabilities

2020

View full text Add to dashboard Cite

With the rise of Internet of Things (IoT), low-cost resource-constrained devices have to be more capable than traditional embedded systems, which operate on stringent power budgets. In order to add new capabilities such as learning, the power consumption planning has to be revised. Approximate computing is a promising paradigm for reducing power consumption at the expense of inaccuracy introduced to the computations. In this paper, we set forth approximate computing features of a processor that will exist in the next generation low-cost resource-constrained learning IoT devices. Based on these features, we design an approximate IoT processor which benefits from RISC-V ISA. Targeting machine learning applications such as classification and clustering, we have demonstrated that our processor reinforced with approximate operations can save power up to 23% for ASIC implementation while at least 90% top-1 accuracy is achieved on the trained models and test data set.

show abstract

Section: Exact Addition/subtraction and Approximate Multiplicationmentioning

confidence: 99%

Approximate CPU Design for IoT End-Devices with Learning Capabilities

2020

View full text Add to dashboard Cite

show abstract

“…However, we found that using different truncation operators such as Floor, Round, and Ceil to truncate the output of truncated multipliers of a design can reduce the magnitude of error and improve the error statistics in some cases. For instance, if we split and of an 11-bit multiplier into chunks of 5, 3, and 3-bit segments and use Round operator to truncate the outputs of small segment multipliers, the maximum value of the magnitude of error will be 3 (out of 2 11 ) and it occurs in 164 instances of × (out of the 2 11 × 2 11 combinations of and ). However, if we use a combination of the truncation operators, the same maximum error will occur just 13 times.…”

Section: Sources Of Approximation Error and Correction Approachmentioning

confidence: 99%

“…"EvoApprox8b" is an open source library that provides several 8-bit approximate adders and multipliers without considering FPGA fabric [10]. By randomly selecting multipliers from [10], the authors in [11] showed that ASIC-based approximate designs offer minimal savings when they are ported to FPGA platforms. Ullah et al in [1] exploited the FPGA fabric and proposed approximate 4 × 2 and 4 × 4 multipliers as basic blocks for designing higher-order multipliers.…”

mentioning

confidence: 99%

Hybrid binary-unary truncated multiplication for DSP Applications on FPGAs

Faraji

Bazargan

2020

Proceedings of the 39th International Conference on Computer-Aided Design

View full text Add to dashboard Cite

“…Most of the architectures in the literature, approximate fixed word-length multipliers or dividers, or SIMD multipliers [8,23,28,29]. These techniques are not generic since approximation principles (as defined for ASIC) neglect differences in the underlying reconfigurable infrastructure and yield insignificant improvements when directly synthesized and ported to FPGAs [31]. Few designs have targeted FPGAs which are either approximate SISD [30,31] or accurate SIMD multipliers [15,18,[24][25][26].…”

Section: Introductionmentioning

confidence: 99%

SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy

Ebrahimi

Ullah

Kumar

2020

Proceedings of the 2020 on Great Lakes Symposium on VLSI

Self Cite

View full text Add to dashboard Cite

The ever-increasing quest for data-level parallelism and variable precision in ubiquitous multimedia and Deep Neural Network (DNN) applications has motivated the use of Single Instruction, Multiple Data (SIMD) architectures. To alleviate energy as their main resource constraint, approximate computing has re-emerged, albeit mainly specialized for their Application-Specific Integrated Circuit (ASIC) implementations. This paper, presents for the first time, an SIMD architecture based on novel multiplier and divider with tunable accuracy, targeted for Field-Programmable Gate Arrays (FPGAs). The proposed hybrid architecture implements Mitchell's algorithms and supports precision variability from 8 to 32 bits. Experimental results obtained from Vivado, multimedia and DNN applications indicate superiority of proposed architecture (both SISD and SIMD) over accurate and state-of-the-art approximate counterparts. In particular, the proposed SISD divider outperforms the accurate Intellectual Property (IP) divider provided by Xilinx with 4× higher speed and 4.6×less energy and tolerating only <0.8% error. Moreover, the proposed SIMD multiplier-divider supersede accurate SIMD multiplier by achieving up to 26%, 45%, 36%, and 56% improvement in area, throughput, power, and energy, respectively.

show abstract

SMApproxLib: Library of FPGA-based Approximate Multipliers

Cited by 46 publications

References 9 publications

Approximate CPU Design for IoT End-Devices with Learning Capabilities

Approximate CPU Design for IoT End-Devices with Learning Capabilities

Hybrid binary-unary truncated multiplication for DSP Applications on FPGAs

SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy

Contact Info

Product

Resources

About