Proceedings of the 39th International Conference on Computer-Aided Design 2020
DOI: 10.1145/3400302.3415700
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Hybrid binary-unary truncated multiplication for DSP Applications on FPGAs

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Cited by 3 publications
(4 citation statements)
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“…When the magnitude of quantization residual is 1, only isZero=1 needs to be coded; when the magnitude of quantization residual is 2, isZero=0 and isOne=1 are written into bitstream; the magnitude of quantization residual is >2, and needs to be encoded, after that the magnitude of quantization residual is subtracted by 1 and encoded by using the Exponential Golomb encoder 45 . For zero quantized residual, the number of consecutive zero is encoded using Truncated Unary coding 46 combined with Exponential Golomb coding.…”
Section: Proposed Methodsmentioning
confidence: 99%
“…When the magnitude of quantization residual is 1, only isZero=1 needs to be coded; when the magnitude of quantization residual is 2, isZero=0 and isOne=1 are written into bitstream; the magnitude of quantization residual is >2, and needs to be encoded, after that the magnitude of quantization residual is subtracted by 1 and encoded by using the Exponential Golomb encoder 45 . For zero quantized residual, the number of consecutive zero is encoded using Truncated Unary coding 46 combined with Exponential Golomb coding.…”
Section: Proposed Methodsmentioning
confidence: 99%
“…It is widely utilized in digital signal processing, linear algebra, cryptosystems, and 3D graphic accelerators. [22][23][24] Column compression (CC) multipliers are composed of three phases: (1) partial product generation; (2) partial product reduction; and (3) final addition. The long critical path of a multiplier has always been a severe challenge for VLSI system designers.…”
Section: Introductionmentioning
confidence: 99%
“…A multiplier is an arithmetic unit with a considerable impact on the performance of the entire system. It is widely utilized in digital signal processing, linear algebra, cryptosystems, and 3D graphic accelerators 22–24 . Column compression (CC) multipliers are composed of three phases: (1) partial product generation; (2) partial product reduction; and (3) final addition.…”
Section: Introductionmentioning
confidence: 99%
“…It is here, DCT is introduced with the fast algorithm for its computation whose performance is closer to that of KLT compared to the performance of walsh hadamard transform, discrete fourier transform, and hadamard transform. Coding of high-resolution images done successfully by discrete cosine transform (DCT) [11]- [15]. DCT was implemented using doublesize fast fourier transform (FFT) utilizing complex arithmetic conventionally due to the lack of an algorithm…”
Section: Introductionmentioning
confidence: 99%