Approximate CPU Design for IoT End-Devices with Learning Capabilities

Taştan, İbrahim Can; Karaca, Mahmut; Yurdakul, Arda

doi:10.3390/electronics9010125

Cited by 11 publications

(20 citation statements)

References 33 publications

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“…It consists of changing only its 7-step integer instruction pipeline to implement the RV32I ISA instead of the original ISA SPARCV8. e instruction set architecture (ISA) of the original processor LEON3 is changed from SPARCV8 to RISC-V [18], while retaining all other IP cores and resources such as memory, memory controllers, peripheral support, debugging support unit (DSU), synthesis scripts for several FPGAs from different manufacturers, and others.…”

Section: Description Of the Reonv And Leon3 Processorsmentioning

confidence: 99%

An Efficient Lightweight Cryptographic Instructions Set Extension for IoT Device Security

Youssef

Abdelli

Dridi

et al. 2022

Security and Communication Networks

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The Internet of Things is changing all sectors such as manufacturing, agriculture, city infrastructure, and the automotive industry. All these applications ask for secure processors that can be embedded in the IoT devices. Furthermore, these devices are restricted in terms of computing capabilities, memory, and power consumption. A major challenge is how to meet the need for security in such resource-constrained devices. This paper presents a customized version of LEON3, the ReonV RISCV (Reduced Instruction Set Computer-five) processor, dedicated for IoT applications that has strong effective security mechanisms built in at the design stage. Firstly, efficient lightweight cipher designs are elaborated and validated. Then, the proposed cryptographic instructions (PRESENT and PRINCE) are integrated into the default instruction set architecture of the ReonV processor core. The instruction set extensions (ISE) of lightweight cipher modules can be instantiated in software routines exactly as the instructions of the base architecture. A single instruction is needed to implement a full lightweight cryptographic instruction. The customized ReonV RISCV processor is implemented on a Xilinx FPGA platform and is evaluated for Slice LUTs plus FF-pairs, frequency, and throughput. Obtained results show that our proposed concepts not only can achieve good encryption results with high performance and reduced cost but also are secure enough to resist against the most common attacks.

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Section: Description Of the Reonv And Leon3 Processorsmentioning

confidence: 99%

An Efficient Lightweight Cryptographic Instructions Set Extension for IoT Device Security

Youssef

Abdelli

Dridi

et al. 2022

Security and Communication Networks

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“…Approximate computing is a new paradigm where an acceptable error is induced in the computing to achieve more energy-efficient processing [ 28 , 29 , 30 , 31 , 32 , 33 ]. It has been introduced at different system levels [ 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 ], and a large number of approximate arithmetic circuits have been designed to save chip area and energy [ 35 , 38 , 46 , 47 , 48 , 49 , 50 , 51 ]. Multiplication is a very common, but expensive operation, with exact multipliers being large circuits that consume a significant amount of energy.…”

Section: Introductionmentioning

confidence: 99%

An Approximate GEMM Unit for Energy-Efficient Object Detection

Pilipović

Risojević

Božič

et al. 2021

Sensors

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Edge computing brings artificial intelligence algorithms and graphics processing units closer to data sources, making autonomy and energy-efficient processing vital for their design. Approximate computing has emerged as a popular strategy for energy-efficient circuit design, where the challenge is to achieve the best tradeoff between design efficiency and accuracy. The essential operation in artificial intelligence algorithms is the general matrix multiplication (GEMM) operation comprised of matrix multiplication and accumulation. This paper presents an approximate general matrix multiplication (AGEMM) unit that employs approximate multipliers to perform matrix–matrix operations on four-by-four matrices given in sixteen-bit signed fixed-point format. The synthesis of the proposed AGEMM unit to the 45 nm Nangate Open Cell Library revealed that it consumed only up to 36% of the area and 25% of the energy required by the exact general matrix multiplication unit. The AGEMM unit is ideally suited to convolutional neural networks, which can adapt to the error induced in the computation. We evaluated the AGEMM units’ usability for honeybee detection with the YOLOv4-tiny convolutional neural network. The results implied that we can deploy the AGEMM units in convolutional neural networks without noticeable performance degradation. Moreover, the AGEMM unit’s employment can lead to more area- and energy-efficient convolutional neural network processing, which in turn could prolong sensors’ and edge nodes’ autonomy.

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“…As an example, the approximate computing is known as a powerful technique that relaxes the constraint of an exact computation, in order to trade the quality of the result with speed, area, and energy consumption [5][6][7]. As recently demonstrated in a plethora of papers [5][6][7][8][9][10][11][12][13][14][15][16][17][18], employing approximate arithmetic data-paths obviously introduces errors in the performed computations, but allows the computational time, the energy consumption, and the resources requirements to be reduced, thus ensuring a good quality-energy trade-off to be achieved.…”

Section: Introductionmentioning

confidence: 99%

“…Indeed, due to their flexibility, run-time reconfigurability, and short time-to-market, FPGA devices are widely recognized as efficient realization platforms for all the above-cited emerging applications. For this reason, researchers have recently focused their attention on specific design techniques aimed to efficiently exploit the approximate computing within FPGA devices [16][17][18].…”

Section: Introductionmentioning

confidence: 99%

“…The inexact addition also provides the carry-in to the subsequent precise sub-adder. In contrast to the approximate adders existing in the literature and suitable for FPGA-based designs, here referenced as the competitors [13,[16][17][18], each couple of consecutive sum bits are computed taking their internal intermediate carry signal into account in an efficient way. As demonstrated in the following, due to this, the novel addition technique introduces computation errors that are significantly lower than those of its counterparts.…”

Section: Introductionmentioning

confidence: 99%

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Efficient Approximate Adders for FPGA-Based Data-Paths

et al. 2020

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Approximate computing represents a powerful technique to reduce energy consumption and computational delay in error-resilient applications, such as multimedia processing, machine learning, and many others. In these contexts, designing efficient digital data-paths is a crucial concern. For this reason, the addition operation has received a great deal of attention. However, most of the approximate adders proposed in the literature are oriented to Application Specific Integrated Circuits (ASICs), and their deployment on different devices, such as Field Programmable Gate Arrays (FPGAs), appears to be unfeasible (or at least ineffective). This paper presents a novel approximate addition technique thought to efficiently exploit the configurable resources available within an FPGA device. The proposed approximation strategy sums the k least significant bits two-by-two by using 4-input Look-up-Tables (LUTs), each performing a precise 2-bit addition with the zeroed carry-in. In comparison with several FPGA-based approximate adders in the existing literature, the novel adder achieves markedly improved error characteristics without compromising either the power consumption or the delay. As an example, when implemented within the Artix-7 xc7a100tcsg324-3 chip, the 32-bit adder designed as proposed here with k = 8 performs as fast as its competitors and reduces the Mean Error Distance (MED) by up to 72% over the state-of-the-art approximate adders, with an energy penalty of just 8% in the worst scenario. The integration of the new approximate adder within a more complex application, such as the 2D digital image filtering, has shown even better results. In such a case, the MED is reduced by up to 97% with respect to the FPGA-based counterparts proposed in the literature.

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Approximate CPU Design for IoT End-Devices with Learning Capabilities

Cited by 11 publications

References 33 publications

An Efficient Lightweight Cryptographic Instructions Set Extension for IoT Device Security

An Efficient Lightweight Cryptographic Instructions Set Extension for IoT Device Security

An Approximate GEMM Unit for Energy-Efficient Object Detection

Efficient Approximate Adders for FPGA-Based Data-Paths

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