Single-transistor latch in SOI MOSFETs

Chen, C.-D.; Matloubian, M.; Sundaresan, R.; Mao, B.-Y.; Wei, C.C.; Pollack, G.

doi:10.1109/55.20420

Cited by 172 publications

(33 citation statements)

References 4 publications

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“…The balance between generation and recombination is crucial in what is essentially the "base" of an equivalent bipolar transistor under extremely high injection conditions and no base contact. This phenomenon of transistor not being able to turn off has been previously reported and analyzed for fully and partially depleted INV devices operating at high drain bias 15,16,18,19 but not for JNL devices. The higher sensitivity of steep S-slope junctionless MOSFET on film and oxide thickness coupled with the challenge of fabrication of high quality defect free thin mono-crystalline silicon film imposes severe limitations on the usefulness of the steep S-slope junctionless transistor.…”

Section: (A)-4(c) As Shown Inmentioning

confidence: 94%

“…This positive feedback mechanism actuates the parasitic "bipolar" effect in parallel, resulting in the sharp increase of drain current. [9][10][11][12][13][14][15][16][17][18][19] In the reverse sweep mode, i.e., In order to understand hysteresis effect in JNL devices, potential distribution, electron, and hole concentration, along a cut-line (shown in Fig. 3(a)) from…”

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confidence: 99%

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Bipolar effects in unipolar junctionless transistors

et al. 2012

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Section: (A)-4(c) As Shown Inmentioning

confidence: 94%

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confidence: 99%

Bipolar effects in unipolar junctionless transistors

et al. 2012

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“…However, the floating body of an SOI MOSFET results in other problems, such as drain-current kink effect, low breakdown voltage [4], and latch effect due to the lateral parasitic bipolar junction transistor (BJT) [5]. Even though fully depleted SOI can reduce the kink effect, very thin Si film may lead to parasitic BJT effects.…”

Section: Introductionmentioning

confidence: 99%

Inversion-layer induced body current in SOI MOSFETs with body contacts

Lin

Chang

2003

IEEE Electron Device Lett.

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This letter investigates the body current of thin silicon-on-insulator MOSFETs with body contacts using H-gate and T-gate structures. Due to tunneling between the inversion layer and body contacts, the extra body current was measured and confirmed by the floating-source measurement techniques The drain current at saturation is increased due to the extra body current, which may result in smaller output resistance. A measurement example is also demonstrated

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“…Partially-depleted SO1 transistors are susceptible to snapback [2] or singletransistor latch [3], which tends to worsen with temperature. Our design uses butting n+ and p+ regions on the source side to alleviate these floating body effects.…”

Section: Technologymentioning

confidence: 99%

“…The nominal gate length is 1.6 pm as defined by the spacing between the n-extended-drain and the n+ source. The effective channel width is over 150 mm.Partially-depleted SO1 transistors are susceptible to snapback [2] or singletransistor latch [3], which tends to worsen with temperature. Our design uses butting n+ and p+ regions on the source side to alleviate these floating body effects.…”

mentioning

confidence: 99%

A 90 V breakdown high temperature SOI lateral power nMOSFET

Tsang¹,

McKitterick²,

Zolnier³

et al.

1998 Fourth International High Temperature Electronics Conference. HITEC (Cat. No.98EX145)

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A high-temperature lateral power MOS field-effect transistor on siliconon-insulator (SOI) material has been demonstrated to operate up to at least 3000C.resistances. This design has only one level of metal (1.5-pm thick AVl%Si), using TiW as a barrier between the silicide and aluminum. The whole FET is passivated This device is targeted initially for hightemperature applications such as engine control and down-hole oil exploration. This power device is easily integrable in our standard digital process flow, enabling high temperature, mixed-signal technology. Prototype solenoid drivers and torque motor drivers have been demonstrated using this technology. TECHNOLOGYThe power device is fabricated using the AUiedSignal 1.25-micron SO1 CMOS process [l]. The starting material (Unibond) is manufactured by SOITEC. The silicon thickness is 0.34 pm atop a 1-pm thick buried oxide. After the island, pwell, n-type extended drain, and field dielectric are defined, a 22.5-nm thick gate oxide is grown in steam, followed by the deposition of POCls-doped LPCVD polysilicon. The nominal gate length is 1.6 pm as defined by the spacing between the n-extended-drain and the n+ source. The effective channel width is over 150 mm.Partially-depleted SO1 transistors are susceptible to snapback [2] or singletransistor latch [3], which tends to worsen with temperature. Our design uses butting n+ and p+ regions on the source side to alleviate these floating body effects.The process also employs 100-nm of cobalt salicide to lower gate and source/drain 0-7803-4540-1/98/$10.00 0 1998 IEEE with 0.8 pm of nitride and 0.3 both deposited using a low-temperature plasma method. of oxide, To achieve a high blocking voltage, we use a lightly-doped n-type extended drain and terminate the polysilicon gate on a thicker field oxide on the drain side. Figure 1 shows a cross-section of the transistor.

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Single-transistor latch in SOI MOSFETs

Cited by 172 publications

References 4 publications

Bipolar effects in unipolar junctionless transistors

Bipolar effects in unipolar junctionless transistors

Inversion-layer induced body current in SOI MOSFETs with body contacts

A 90 V breakdown high temperature SOI lateral power nMOSFET

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