Single-Event-Upset (SEU) Awareness in FPGA Routing

Golshan,; Bozorgzadeh,

doi:10.1109/dac.2007.375181

Cited by 8 publications

(9 citation statements)

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“…Modern FPGA has shifted to the multiplexer-based (MUXbased) unidirectional routing architecture [6] [7], where the fault mechanism is different from conventional bidirectional routing as in the previous studies [8] [9]. In this paper, considering MUX-based unidirectional routing, we formulate an InPlace inVersion (IPV) of LUT logic polarities to reduce interconnect SER, and reveal a locality and NP-Hardness of the IPV problem.…”

Section: Introductionmentioning

confidence: 99%

Mitigating FPGA interconnect soft errors by in-place LUT inversion

Jing¹,

Lee²,

He³

et al. 2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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-Modern SRAM-based FPGAs (Field Programmable Gate Arrays) use multiplexer-based unidirectional routing, and SRAM configuration cells in these multiplexers contribute to the majority of soft errors in FPGAs. In this paper, we formulate an In-Placed inVersion (IPV) on LUT (Look-Up Table) logic polarities to reduce the Soft Error Rate (SER) at chip level, and reveal a locality and NP-Hardness of the IPV problem. We then develop an exact algorithm based on the binary integer linear programming (ILP) and also a heuristic based on the simulated annealing (SA), both enabled by the locality. We report the results for 10 largest MCNC combinational benchmarks synthesized by ABC and then placed and routed by VPR. The results show that IPV obtains close to 4x chip level SER reduction on average and SA is highly effective by obtaining the same SER reduction as ILP does. In addition, IPV does not change placement and routing, and does not affect design closure. To the best of our knowledge, it is the first in-depth study on SER reduction for modern multiplexer-based FPGA routing by in-placed logic re-synthesis.

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Section: Introductionmentioning

confidence: 99%

Mitigating FPGA interconnect soft errors by in-place LUT inversion

Jing¹,

Lee²,

He³

et al. 2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…In addition, these existing fault estimation approaches and fault mitigation approaches (e.g., [Sterpone et al 2006;Golshan et al 2007;Asadi et al 2005;Krishnaswamy et al 2007]) all assume a bidirectional routing architecture. However, modern FPGA routing has shifted from the conventional bidirectional routing towards unidirectional routing architecture [Lemieux et al 2004;Luu et al 2009;Smith et al 2009].…”

Section: Failure Rate Estimationmentioning

confidence: 99%

“…SEU on Bidirectional Routing. Conventionally, inter-CLB routing is typically interconnected via bidirectional pass transistors [Sterpone et al 2006;Golshan et al 2007], and its connectivity within a connection box or a switch box is configured by CRAM bits. Once affected by an SEU, these bits either Temporarily Stuct-At-0 (TSA0) or Stuct-At-1 (TSA1).…”

Section: Seu Fault Overview In Fpgamentioning

confidence: 99%

“…Although modern FPGAs are capable of more powerful designs benefiting from the continuous technology scaling, they also become more sensitive to soft errors due to a large amount of SRAM cells used for their configurability. Suffering from the soft errors caused by cosmetic radiation or circuit internal noise [Sterpone et al 2006], the fault sensitivity of these SRAM cells increases due to technology scaling by smaller feature size, higher logic density and lower operating voltage [Golshan et al 2007]. The effect causes so called SEUs (single event upset) that change the logic state of a SRAM cell bit and may lead to functional failures of the implemented applications on FPGAs.…”

Section: Introductionmentioning

confidence: 99%

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SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms

Jing

Lee

Feng

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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Reliability has become an increasingly important concern for SRAM-based field programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based FPGAs, this article first develops an SEU evaluation framework that can quantify the failure sensitivity for each configuration bit during design time. This framework considers detailed fault behavior and logic masking on a post-layout FPGA application and performs logic simulation on various circuit elements for fault evaluation. Applying this framework on MCNC benchmark circuits, we first characterize SEUs with respect to different FPGA circuits and architectures, for example, bidirectional routing and unidirectional routing. We show that in both routing architectures, interconnects not only contribute to the lion's share of the SEU-induced functional failures, but also present higher failure rates per configuration bits than LUTs. Particularly, local interconnect multiplexers in logic blocks have the highest failure rate per configuration bit. Then, we evaluate three recently proposed SEU mitigation algorithms, IPD, IPF, and IPV, which are all logic resynthesis-based with little or no overhead on placement and routing. Different fault mitigating capabilities at the chip level are revealed, and it demonstrates that algorithms with explicit consideration for interconnect significantly mitigate the SEU at the chip level, for example, IPV achieves 61% failure rate reduction on average against IPF with about 15%. In addition, the combination of the three algorithms delivers over 70% failure rate reduction on average at the chip level. The experiments also reveal that in order to improve fault tolerance at the chip level, it is necessary for future fault mitigation algorithms to concern not only LUT or interconnect faults, but also their interactions. We envision that our framework can be used to cast more useful insights for more robust FPGA circuits, architectures, and better synthesis algorithms.

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“…An alternative to the complete replication of a design is to reduce the sensitivity to soft errors in the user's design by careful selection of the resources used. For example, in [87] an FPGA router that considers the number of sensitive configuration bits (i.e., the number of bits that must be set correctly for the circuit to function) was created. The router considers these bit counts in addition to delay.…”

Section: Configuration Memorymentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

317

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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Single-Event-Upset (SEU) Awareness in FPGA Routing

Cited by 8 publications

References 0 publications

Mitigating FPGA interconnect soft errors by in-place LUT inversion

Mitigating FPGA interconnect soft errors by in-place LUT inversion

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms

FPGA Architecture: Survey and Challenges

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