Mitigating FPGA interconnect soft errors by in-place LUT inversion

Jing, Jing; Lee, Myeong Soo; He, Ying; Mao,

doi:10.1109/iccad.2011.6105389

Cited by 13 publications

(4 citation statements)

References 14 publications

(17 reference statements)

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“…Many researchers have proposed different techniques to manage soft errors in FPGAs. [10][11][12][13][14][15] Adewale Adetomi et al [10], designed ICAP Controller with a selective-area soft error Mitigation Engine. They tried to scan selective-area of the FPGA instead of entire device which saved them the time available for reconfiguration.…”

Section: Previous Related Workmentioning

confidence: 99%

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Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation

S¹,

Dinesha²,

Shashikala³

et al. 2020

IJCNIS

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Designing a reliable system on reconfigurable devices has become a significant factor for implementing mission critical applications like communication protocols, automotive, nuclear reactor control, and remote applications. With the improvement in fabrication technology, logic density of the field programmable gate arrays has increased rapidly. Because of decrease in feature size, integrated circuits are becoming vulnerable to errors and also the ageing component results in run time faults. FPGAs when used in harsh conditions like high radiation and temperatures, there is a possibility of getting affected by transient faults or the soft errors. In digital communication, safety and confidentiality of data is achieved through a suitable encryption algorithm. Encryption is most important aspect when it comes to security. Reliable design techniques are very much necessary for maintaining the system's normal function. Many of the available techniques are based on redundancy logic causing area overhead for the design. Through this paper, an implementation is illustrated for managing soft errors or the single event upsets. Proposed methodology identifies and avoids the errors occurring at the logic resources where the encryption algorithms are mapped on the device. Thus encryption algorithms work normally without getting affected by the errors. During the simulation process, errors are injected at the configuration memory frames and monitored using a Single event-upset manager (SEM) controller. The proposed design is implemented on Zedboard using Xilinx Vivado 2017.4.

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Section: Previous Related Workmentioning

confidence: 99%

“…Fault identification was done as an application execution profiling. Naifeng Jing1et al, [15] have considered soft error management across routing of FPGAs. They developed a masking mechanism for managing faults.…”

Section: Previous Related Workmentioning

confidence: 99%

Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation

S¹,

Dinesha²,

Shashikala³

et al. 2020

IJCNIS

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“…Recently, several logic resynthesis-based SEU mitigation techniques have been proposed, such as ROSE [Hu et al 2008], IPR [Feng et al 2009], IPD , R2 [Jose et al 2010], IPF [Feng et al 2011], and IPV [Jing et al 2011b], which apply different logic masking strategies to mitigate the fault impact with minimum overhead in area, power, and performance. Applied on non-mission-critical FPGA applications, such as networking and communication, these algorithms can reduce SEU-induced failure rates on an LUT or interconnect significantly.…”

Section: Resynthesis-based Fault Mitigation Algorithmsmentioning

confidence: 99%

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms

Jing

Lee

Feng

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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Reliability has become an increasingly important concern for SRAM-based field programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based FPGAs, this article first develops an SEU evaluation framework that can quantify the failure sensitivity for each configuration bit during design time. This framework considers detailed fault behavior and logic masking on a post-layout FPGA application and performs logic simulation on various circuit elements for fault evaluation. Applying this framework on MCNC benchmark circuits, we first characterize SEUs with respect to different FPGA circuits and architectures, for example, bidirectional routing and unidirectional routing. We show that in both routing architectures, interconnects not only contribute to the lion's share of the SEU-induced functional failures, but also present higher failure rates per configuration bits than LUTs. Particularly, local interconnect multiplexers in logic blocks have the highest failure rate per configuration bit. Then, we evaluate three recently proposed SEU mitigation algorithms, IPD, IPF, and IPV, which are all logic resynthesis-based with little or no overhead on placement and routing. Different fault mitigating capabilities at the chip level are revealed, and it demonstrates that algorithms with explicit consideration for interconnect significantly mitigate the SEU at the chip level, for example, IPV achieves 61% failure rate reduction on average against IPF with about 15%. In addition, the combination of the three algorithms delivers over 70% failure rate reduction on average at the chip level. The experiments also reveal that in order to improve fault tolerance at the chip level, it is necessary for future fault mitigation algorithms to concern not only LUT or interconnect faults, but also their interactions. We envision that our framework can be used to cast more useful insights for more robust FPGA circuits, architectures, and better synthesis algorithms.

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“…Accordingly, there are many techniques proposed to mitigate SEUs [3][4][5]. There are some suggested techniques to reduce SEU effects such as Triple Modular Redundancy (TMR) [6] and Error Correcting Codes (ECC) [7].…”

Section: Introductionmentioning

confidence: 99%

Dynamic fault recovery using partial reconfiguration for highly reliable FPGAs

Alkady

El-Araby

Abdelhalim

et al. 2015

2015 4th Mediterranean Conference on Embedded Computing (MECO)

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FPGAs are becoming more popular in the domain of safety-critical applications (such as space applications) due to their high performance, re-programmability and reduced development cost. Such systems require FPGAs with selfdetection and self-repairing capabilities in order to cope with errors due to the harsh conditions that usually exist in such environments. In this paper, a new dynamic fault recovery technique is proposed using the runtime partial reconfiguration (PR) property in FPGAs. It focuses on open interconnect faults and relies on specifying a Partially Reconfigurable block in the FPGA that is only used during the recovery process after the failure of the first module in the system. The technique uses only one location to recover from errors in any of the FPGA's modules. Accordingly, it requires less area overhead when compared to other techniques.

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Mitigating FPGA interconnect soft errors by in-place LUT inversion

Cited by 13 publications

References 14 publications

Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation

Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms

Dynamic fault recovery using partial reconfiguration for highly reliable FPGAs

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