Single event transient pulse widths in digital microcircuits

Gadlage, Matthew J.; Schrimpf, R.D.; Benedetto, J.M.; Eaton, P.H.; Mavis, D.G.; Sibley, Mike; Avery, Keith; Turflinger, T.L.

doi:10.1109/tns.2004.839174

Cited by 124 publications

(23 citation statements)

References 11 publications

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“…As expected, this also confirms that larger LETs result in larger pulse widths. It is interesting to note that the SET pulse widths predicted from these simulations are relatively smaller than observed for earlier technology nodes in [1][7] [9]. Although a direct comparison with transient current measurements reported in [8] cannot be made because of very large size devices under test and a different technology used in that work (50nm), our simulations agree with the trend that SET pulse widths are getting smaller in sub-100nm technologies.…”

Section: Set Pulse Widths For Large Letssupporting

confidence: 77%

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Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Naseer

Draper

Boulghassoul

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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This work presents an efficient hybrid simulation approach, developed for accurate characterization of single-event transients (SETs) in combinational logic. Using this approach, we show that charges as small as 3.5fC can introduce transients in commercial 90nm CMOS technology, hence increasing the likelihood of SETinduced soft errors. SET pulse-widths as large as 942ps are predicted at an LET (Linear Energy Transfer) of 60MeV-cm 2 /mg. Process-corner variations are shown to modulate SET pulse-widths by up-to 75%. The results suggest that selection of mitigation techniques for SET radiation-hardened circuits cannot exclusively rely on baseline process analyses, as they might grossly underestimate the true SET risk to the design.

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Section: Set Pulse Widths For Large Letssupporting

confidence: 77%

“…Numerous efforts have been made to indirectly characterize SETs through experimentation [1][7] [9]. A more recent effort by FerletCavrois et al [8] succeeded in measuring transient current pulses on relatively large devices in real-time conditions.…”

Section: Introductionmentioning

confidence: 99%

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Naseer

Draper

Boulghassoul

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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show abstract

“…However, recent in-depth studies have concluded that SET pulses can be much larger than this. While particle strikes with linear energy transfer (LET) of 5-10 MeV-cm /mg often produce 100-200 ps pulses, cosmic ray strikes with LET of 100 MeV-cm /mg can induce SET pulses up to 2 ns long [12]- [14]. In general, SET pulse widths increase linearly with increasing LET from particle strikes [15].…”

Section: Schemes For Eliminating Transient-widthmentioning

confidence: 99%

Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems

Blum

Delgado-Frias

2006

IEEE Trans. Nucl. Sci.

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Abstract-In the presence of radiation, particle strikes can cause temporary signal errors in ICs. Particle strikes that directly affect memory are known as single event upsets (SEUs), while strikes that affect combinational logic and spread to memory are called single event transients (SETs). In this paper, we propose two novel approaches to hardening integrated circuits against SEUs and SETs. The proposed approaches are fully-differential dual-interlocked storage cell (DICE) and triple path DICE (TPDICE).The fully-differential DICE and TPDICE approaches are compared against two existing approaches, which are triple modular redundancy (TMR) and basic SET-tolerant DICE. All approaches except for the basic SET-tolerant DICE scheme share a common theme, which is the ability to bypass SEUs and SETs. This is critical for performance, as it allows the system to proceed with subsequent operations while a cell is recovering from the effects of a particle strike. SET pulse widths can be substantial (up to 2 ns), and so high-performance systems cannot afford to pause operations while these pulses are present. The minimum clock periods obtained for the basic SET-tolerant approach were 515 ps with no SET, and 1310 ps with a 500 ps SET (in 0.18 m CMOS). In contrast, the clock periods for the bypass-capable approaches with no SET/500 ps SET were 628/749 ps for TMR, 348/480 ps for fully-differential DICE, and 434/552 ps for TPDICE. Among the approaches that bypass transient pulses, TPDICE is the most balanced. TMR suffers from overhead due to its need for external voting circuitry. In addition to this, fully-differential DICE cannot be used with combinational logic, while TPDICE can.

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“…Since drive strength is fixed for a given circuit, higher LETs will create a longer t SET . t SET has been shown to increase with decreasing process sizes [7][8] thus increasing the importance of SETs in ICs as technology processes progress.…”

Section: ) Single Event Transientsmentioning

confidence: 99%

Redundancy Based on a Fault-Tolerant Gate Array Cell

Tyurin¹,

Kamenskih²

2017

VVSUTR

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Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets (SEU), and single event transients (SET) are increasingly becoming a concern. While numerous methods currently exist to nullify SEUs and SETs,

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Single event transient pulse widths in digital microcircuits

Cited by 124 publications

References 11 publications

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems

Redundancy Based on a Fault-Tolerant Gate Array Cell

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