Single-event multiple transients in guard-ring hardened inverter chains of different layout designs

Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

“…On the basis of this method, Huang et al [8] proposed a structure that can simultaneously measure multiple transient pulses, using eight capture circuits to share a self-trigger structure design, which can measure the SEMT. This improvement has also been widely used by researchers [6,10,18].…”

“…As process feature sizes continue to shrink, clock frequencies continue to increase, node capacitance and supply voltage decrease, the critical charge of transient pulses is reduced [3][4][5], and waveforms are more easily captured and soft errors are formed. It has been reported that SET are the main cause of soft errors in space applications [6,7], and charge sharing may even affect multiple nodes and cause single-event multiple transients (SEMT) [8][9][10]. These problems are already common in combinatorial logic circuits.…”

Exploiting Transistor Folding Layout as RHBD Technique Against Single-Event Transients

“…HE susceptibility to energetic particles increases as the transistor feature size is reduced [1][2][3]. Due to the extensive usage of electronics systems in harsh environments, mitigation techniques against radiation effects have been vastly investigated in literature [4][5][6][7]. Radiation hardening strategies can be explored from fabrication process modifications to different design implementations.…”

“…The generation mechanisms of Single-Event Effects (SEEs) are strongly connected to the physical layout of integrated circuits (ICs), as, for example, the relation between the energy deposition and charge collection in the p-n junctions of transistors. Accordingly, several hardening approaches can be applied at circuit layout level such as the Enclosed Layout Transistor (ELT), guard rings, dummy transistors/gate or Dual Interlocked Storage Cells (DICE) [6][7][8][9]. The general goal of each technique is to reduce the charge collection efficiency of a given circuit so the overall Single-Event Transient (SET) pulse can be shortened and/or the collected charge does not exceed the critical charge.…”

“…However, due to the multi-node collection at deeply scaled technologies, the charge sharing effect might also reduce the efficiency of well-known RHBD schemes such as the DICE designs and Error-Correction Codes (ECCs) due to multiple Single-Event Upset (SEU) and multiple SET occurrences [10]. Some investigation has been done towards the adoption of transistor folding technique as radiation hardening approach [6,[11][12][13]. Device level simulations and laser testing have shown a reduction on the SET susceptibility of single transistors and inverters [6,[11][12][13].…”