2020
DOI: 10.1109/tns.2020.3003166
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Exploiting Transistor Folding Layout as RHBD Technique Against Single-Event Transients

Abstract: Radiation hardening techniques can be extensively used in the design level to improve the robustness of VLSI circuits used in space applications. Accordingly, this work analyzes the efficiency of transistor folding layout in improving the Single-Event Transient robustness of digital circuits. Additionally, diffusion splitting is proposed to reduce the area overhead of multiple-finger designs. Besides increasing threshold Linear Energy Transfer, results show that both techniques can also reduce the overall cros… Show more

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Cited by 6 publications
(2 citation statements)
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“…13, (a) a layout of an arbitrary transistor of sizing 2W without transistor folding technique, and (b) an equivalent transistor with a layout using folding to reduce the height of the cell (note that the height is half of the unfolded design). Aguiar et al [21] present a study of the effects of transistor folding in three logic gates (INV, NAND, NOR). Although, these folded logic gates have shown improved SET rate, the authors claim that, similarly to other circuit techniques, its efficiency is input dependent and should be carefully assessed for the specific application radiation environment and operation conditions.…”
Section: Logic Gate Layoutmentioning
confidence: 99%
“…13, (a) a layout of an arbitrary transistor of sizing 2W without transistor folding technique, and (b) an equivalent transistor with a layout using folding to reduce the height of the cell (note that the height is half of the unfolded design). Aguiar et al [21] present a study of the effects of transistor folding in three logic gates (INV, NAND, NOR). Although, these folded logic gates have shown improved SET rate, the authors claim that, similarly to other circuit techniques, its efficiency is input dependent and should be carefully assessed for the specific application radiation environment and operation conditions.…”
Section: Logic Gate Layoutmentioning
confidence: 99%
“…7,8) Layout-based radiation hardening techniques can alleviate the single-event effect to some extent for both N-type metal-oxide-semiconductor (NMOS) and P-type metal-oxide-semiconductor (PMOS). [9][10][11] Some reported work has shown that the transistor stacking causes a SET cross-section reduction of about 66.3% at 2.5 MeV•cm 2 mg −1 for the NOR logic gate, 12) and 18.6% reduction of SET pulse width is obtained in inverter by adjusting the NMOS transistor placement. 13) Although the hardened designs decrease the effects of SET on standard cells, the results mainly reflect an average level.…”
Section: Introductionmentioning
confidence: 99%