This paper investigates the original circuit theory on stopband (SB) negative group delay (NGD) passive topology. The basic specifications of SB-NGD function are defined by considering the voltage transfer function (VTF) of the passive circuit. An original design method and experimentation tests of SB-NGD circuit are developed. The innovative theoretical analysis is elaborated from both magnitude and GD analytical expression of the VTF model from the resonant LC-series network passive topology. The mathematical existence condition of SB-NGD aspect is analytically explored in function of R, L, and C component parameters. The formulations of the basic equations enabling the calculation of the lumped components of the SB-NGD passive circuit in function of the desired specifications as NGD cut-off frequencies, NGD value and attenuation are established. To confirm the effectiveness of the original SB-NGD circuit theory, a proof-of-concept (POC) of SB-NGD circuit board is designed, simulated, fabricated, and experimented. As expected, despite the equivalent series resistor (ESR) effect of the inductor element, the theoretical modelling, simulation and measurement results are in good agreement. The SB-NGD behavior is confirmed with lower and upper cut-off frequencies, 0.7 kHz and 1.35 kHz, respectively. Furthermore, the corresponding NGD minimal values are −33 µs and −11 µs, respectively.

International audienceThe charge pump phase locked loop (CP-PLL) is widely used subsystem in modern mixed-signal electronic systems that are utilized in digital and wireless applications such as clock generation, synchronization and frequency synthesis. In the classical mode, the combination of a current switched charge pump and a digital phase and frequency detector (CP-PFD) circuits produces an ideal pulse width modulated constant current during one sampling period, which permits a suitable transient performance. Nevertheless, many commercially used CP-PLL chips (e.g., 4046 family) have a voltage switched charge pump (VSCP) because the design of the constant voltage source is easier than the constant current generator and it is a low cost solution. However, the VSCP delivers a non-constant pump current, which varies during one sampling period related to the electrical load of the loop filter (LF). This effect results in a varying gain of the control system affecting significantly its tracking ability. Furthermore, due to its hybrid structure, the simulation of the CP-PLL at high frequencies is challenging and the analysis of its transient characteristics during its non-linear acquisition procedure is not easy. In this paper, a first ever exact and nonlinear model based on the phase equations of the second order voltage switched charge pump phase locked loop (VSCP-PLL) is established by using an event driven (ED) technique. This exact model is then simplified by using a step-wise quasi-constant current approximation during one sampling period to obtain the analytical phase equations. The derived ED-model is validated at transistor level simulations using 130 nm CMOS process. Furthermore, some typical nonlinear features of the VSCP-PLL are explored and the developed ED-models are compared with the quasi-time-continuous (QTC) theory

A compact reconfigurable CMOS low-noise amplifier (LNA) is presented for applications in DCS1800, UMTS, WLAN-b/g and Bluetooth standards. The proposed LNA features first a current reuse shunt-feedback amplifier for wideband input matching, low-noise figure and small area. Secondly, a cascode amplifier with a tunable active LC resonator is added for high gain and continuous tuning of bands. Fabricated in a 0.13 μm CMOS process, the measured results show >20 dB power gain, <3.5 dB noise figure in the frequency range of 1.8-2.4 GHz, return losses S 11 and S 22 lower than −12 and −14 dB, respectively, with a moderate IIP3 of −11.8 dBm at 2.4 GHz. It consumes 9.6 mW from a 1.2 V supply voltage, while occupying an active silicon area of only 0.052 mm 2 .

This paper focuses on the time-domain analysis of bandpass (BP) negative group delay (NGD) function. The innovative NGD investigation is based on the time-domain experimentation of an innovative topology of "lill"-shape passive microstrip circuit. The design principle of the proof of concept (POC) constituted by particular microstrip shapes is described. The NGD circuit is inspired from a recent fully distributed "li"-topology. Before the time-domain investigation, the BP NGD specifications of the circuit under study are academically defined. As practical application of the basic definition, a frequency domain validation of "lill"-circuit is presented in the first section of the paper. The POC circuit is specified by a -8 ns NGD value at 2.31 GHz NGD center frequency and a 27 MHz NGD bandwidth. The "lill"-circuit exhibits an attenuation loss of about -6.2 dB at the NGD center frequency. Then, the two-port black box model of "lill"-NGD-circuit represented by touchstone data of the measured S-parameters is exploited for the transient simulation. The measured group delay (GD) illustrates that the tested "lill"-circuit operates as a BP function regarding the NGD with NGD equal to -8.1 ns at the NGD center frequency. The timedomain demonstration of the BP NGD function was performed using a gaussian pulse modulating sine carrier. The innovative experimental setup with the possibility to plot simultaneously well synchronized input and output signals is explained. The BP NGD time-domain response is understood from commercial tool simulation using the touchstone S-parameters of the measured "lill"-circuit by using a Gaussian upconverted pulse having a 27 MHz frequency bandwidth. It was observed that the output signals are delayed when the sine carrier is out of NGD-band. However, the output signal envelope is in advanced of about -8 ns when the carrier is tuned to be approximately equal to the 2.31 GHz NGD center frequency. To confirm the time-domain typical behavior of BP NGD response, an input pulse signal having Gaussian waveform were considered during the test. However, the input signal spectrum must be determined in function of the NGD bandwidth. After tests, measured output signal envelopes presenting leading edge, trailing edge and peak in time-advance compared to the input ones are observed experimentally. The results of the present feasibility study open a potential microwave communication application of BP NGD function notably for systems operating with ISM and IEEE 802.11 standards.

In this article, a design methodology of an active bandpass filter (BPF) using tunable active inductor (TAI) achieving wide frequency contiguous tuning range (FTR) is presented. The tunable BPF is realized with a differential TAI (DTAI) employing two‐reconfiguration mechanisms one for coarse‐tuning using a controllable current source while the fine‐tuning is performed through a variable feedback resistance. The center frequency tuning is performed through the variation of the DTAI control voltages. A cross‐coupled pair based negative resistance technique is also applied to compensate the resistive losses of equivalent RLC resonator. The filter performances are significantly improved using several optimization techniques such as voltage scaling and multigate finger techniques. The proposed BPF is simulated using 0.13 μm CMOS technology. The filter achieves an insertion loss (IL) of 26.62‐33.45 dB over the tuning range 1.16‐3.27 GHz with a relative bandwidth of 1.3%‐3.4%. The noise figure and input 1‐dB compression point at 1.84 GHz are 14.93 dB and 2.72 dBm, respectively. The designed RF filter consumes an average power of 5 mW at 1 V supply voltage.

A digitally controlled oscillator (DCO) suitable for multi-standards radio-frequency (RF) operation is presented. It has an LC topology using an active inductor based on CMOS controllable inverters. The tunability of the oscillator frequency is ensured by varying the digital word applied to the inverters' control voltages. The proposed DCO has a small area and exhibits a high-frequency tuning range while achieving low power consumption with good stability against process variations.

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A design methodology of CMOS LC voltage-controlled oscillator (VCO) is proposed in this paper. The relation between components and specifications of the LC-VCO is studied to easily identify its design trade-offs. This methodology has been applied to design ultra-low-power LC-VCOs for different frequency bands. An LC-VCO based on the current reuse technique has been realized with the proposed methodology in 0.13[Formula: see text][Formula: see text]m CMOS process. Measurements present an ultra-low power consumption of only 262[Formula: see text][Formula: see text]W drawn from 1[Formula: see text]V supply voltage. The measured frequency tuning range is about 10% between 2.179[Formula: see text]GHz and 2.409[Formula: see text]GHz. The post-layout simulation presents a phase noise (PN) of [Formula: see text][Formula: see text]dBc/Hz, while the measured PN is [Formula: see text][Formula: see text]dBc/Hz.