Single-chip 1062 Mbaud CMOS transceiver for serial data communication

Ewen, J.F.; Widmer, A.X.; Soyuer, M.; Wrenner, K.R.; Parker, B.; Ainspan, H.

doi:10.1109/isscc.1995.535263

Cited by 29 publications

(4 citation statements)

References 4 publications

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“…Then, Marketos et al [21] demonstrated that ROs can easily lock onto an external periodic signal injected into the ring via the power supply. In their paper, the authors showed that this kind of attack can significantly reduce the entropy rate at the output of the RO-based TRNG and make generated numbers 1 https://gitlab.univ-st-etienne.fr/ugo.mureddu/locking-osicllating-cells.git manipulable. They provide a practical illustration of the attack on an EMV payment card.…”

Section: Related Workmentioning

confidence: 99%

Experimental Study of Locking Phenomena on Oscillating Rings Implemented in Logic Devices

Mureddu

Bochard

Bossuet

et al. 2019

IEEE Trans. Circuits Syst. I

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Oscillating rings are widely used in CMOS logic devices because they are easy to integrate, require low area and low power. Their main disadvantage is that they tend to lock to each other and/or to an external periodic signal. This locking phenomenon can render a system based on a freely running oscillator non-functional. A detailed study of the causes of the phenomenon and how to avoid it, is therefore of paramount importance. In this paper, we conduct a detailed examination of the locking phenomenon using the most commonly used rings: ring oscillators, transient effect ring oscillators and selftimed rings. We then analyze the consequences of locking on different use cases based on oscillating rings and provide design recommendations to minimize its impact. Our results could help designers better anticipate locking phenomenon in their future designs. To ensure reproducibility of the results, the VHDL code of all the experiments is available and can be downloaded from a dedicated web page. Index Terms-Free running oscillators, ring oscillator, transient effect ring oscillator, self-timed ring oscillator, locking phenomenon I. INTRODUCTION Electronic oscillators are key elements in many data processing applications. They are used in communication systems for radio and television signal modulation and demodulation or channel selection. They are also used in most digital circuits as a time reference for synchronizing operations or for serial data communication [1]. PLL based frequency synthesis and clock signal generation are also based on oscillators [2], [3]. In data security applications, oscillators serve as source of entropy for true random number generators (TRNGs) [4], [5] or physical unclonable functions (PUFs) [6], [7]. Ideally, electronic oscillator produces a perfect time reference (i.e. a periodic signal, often with a sine waveform or a square waveform). In practice, all types of oscillators are affected by perturbations and noises, and their output is not perfectly periodic. Numerous types of oscillator circuitries are available, but the principle of operation, the frequency stability and the robustness against variations in environmental conditions like supply voltage, temperature and electromagnetic interference are specific to each. The most commonly used are harmonic oscillators (i.

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Section: Related Workmentioning

confidence: 99%

Experimental Study of Locking Phenomena on Oscillating Rings Implemented in Logic Devices

Mureddu

Bochard

Bossuet

et al. 2019

IEEE Trans. Circuits Syst. I

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“…This section gives a brief overview of the digital functions, concentrating specifically on the deserializer, and the basic approach used to achieve Gb/s data rates. A more detailed discussion can be found in [12], The architecture used in the deserializer is shown in Figure 7. This example is specific to a Fibre Channel link using the 8B/10B code [13], but is easily extended to other environments.…”

Section: Frequency Synthesizer Pllmentioning

confidence: 99%

CMOS circuits for Gb/s serial data communication

Ewen¹,

Soyuer²,

Widmer³

et al. 1995

IBM J. Res. & Dev.

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The functional characteristics and design challenges associated with a variety of communication-related circuits are presented. These include the mixed-signal design and noise issues associated with high-speed clock generation and recovery for serial data communication. Hardware results are presented on the noise properties of common integrated voltage-controlled oscillator (VCO) circuits. introductionA key characteristic of ICs in many communication-related applications is the combination of analog circuits with digital logic, while maintaining maximum performance at minimum power and cost. This combination presents a number of challenges beyond basic circuit design issues, ranging from technology choice and simulation techniques to noise and crosstalk. This paper focuses on recent CMOS design work addressing these issues, with specific attention to the area of high-speed serial data communication.Serial baseband data links, whether using fiber-optic or coaxial cables, incorporate coders and decoders, highspeed multiplexors and demultiplexors, and low-speed clock synchronization, along with phase-locked loops for

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“…The main idea of the PST architecture is to adjust the clock skew dynamically even after a chip has been manufactured. There are two important devices in the PST architecture: adjustable delay buffers (ADBs) [21], [25] and phase detectors (PDs) [25]- [27]. An ADB is a delay buffer whose delay can be modified through the controlling inputs.…”

Section: Introductionmentioning

confidence: 99%

A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning

Kao

Tsai

Chang

2015

IEEE Trans. VLSI Syst.

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Clock skew minimization that is an important issue in very large scale integration design has become difficult due to the presence of process, voltage, and temperature (PVT) variations. The post-silicon skew tuning (PST) technique with the ability to tolerate PVT variations, even after a chip is manufactured has generated considerable discussion. The basic idea of the PST architecture is to minimize the clock skew dynamically. Unlike most previous works that have focused on the implementation and the performance issues of a PST architecture, this paper focuses on the testing issues of a PST architecture. However, testing the variation tolerance ability of the PST architecture is difficult because the clock skew does not directly affect the functionality of a design. In this paper, we propose an efficient fault model considering the physical limitation of the devices for the PST architecture. In addition, we propose some novel structures to detect the manufacturing faults and increase the robustness of a PST architecture. Our experiment shows that with a little increase in overhead, we can achieve robustness.

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Single-chip 1062 Mbaud CMOS transceiver for serial data communication

Cited by 29 publications

References 4 publications

Experimental Study of Locking Phenomena on Oscillating Rings Implemented in Logic Devices

Experimental Study of Locking Phenomena on Oscillating Rings Implemented in Logic Devices

CMOS circuits for Gb/s serial data communication

A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning

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