Abstract:Clock skew minimization that is an important issue in very large scale integration design has become difficult due to the presence of process, voltage, and temperature (PVT) variations. The post-silicon skew tuning (PST) technique with the ability to tolerate PVT variations, even after a chip is manufactured has generated considerable discussion. The basic idea of the PST architecture is to minimize the clock skew dynamically. Unlike most previous works that have focused on the implementation and the performan… Show more
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