This work implements the media independent functions specified in the emerging ANSI fibre channel standard at 1062.5Mbaud. Integrated onto a single CMOS chip are: two phase-locked loops (PLL) for clockgeneration and clockrecovery, a selectable 1B or 2B parallel interface with corresponding multiplexer and demultiplexer for parallel-to-serial and serial-to-parallel conversion, word alignment logic for byte synchronization, 8B/10B coder and decoder, and high-speed differential CMOS PECL drivers and receivers for the serial I/O. The chip measures 3.9 x4.5mm2with 100 I/O and dissipates 1.2W at 1062Mbaud with a 3.6V supply. This design achieves higher-speed operation than previous CMOS work with similar integration, and lower power dissipation with higher integration than bipolar implementations at comparable speeds. [l, 21
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