CMOS circuits for Gb/s serial data communication

Abstract

The functional characteristics and design challenges associated with a variety of communication-related circuits are presented. These include the mixed-signal design and noise issues associated with high-speed clock generation and recovery for serial data communication. Hardware results are presented on the noise properties of common integrated voltage-controlled oscillator (VCO) circuits. introductionA key characteristic of ICs in many communication-related applications is the combination of analog circuits with digital logic, while maintaining maximum performance at minimum power and cost. This combination presents a number of challenges beyond basic circuit design issues, ranging from technology choice and simulation techniques to noise and crosstalk. This paper focuses on recent CMOS design work addressing these issues, with specific attention to the area of high-speed serial data communication.Serial baseband data links, whether using fiber-optic or coaxial cables, incorporate coders and decoders, highspeed multiplexors and demultiplexors, and low-speed clock synchronization, along with phase-locked loops for

A translinear SiGe BiCMOS current-controlled oscillator with 80 Hz–800 MHz tuning range

“…The three most common voltage-controlled oscillator (VCO) topologies that have been mainly exploited, include relaxation VCOs, adjustable delay ring oscillators as well as delay-interpolating ring oscillators [3]. Multiple decade (typically 4-5 decades) frequency control has been demonstrated with both relaxation [4,5] as well as ring oscillators [6,7].…”

Sub-picosecond jitter SiGe BiCMOS transmit and receive PLLs for 12.5 Gbaud serial data communication

“…A conventional type CMOS three-state phase and frequency detector (PFD) is used in the frequency acquisition loop [6]. The Up and Down signals from the PFD are fed directly (via the selector) to the loop filter as differential signals after a CMOS-to-ECL conversion.…”