Sub-picosecond jitter SiGe BiCMOS transmit and receive PLLs for 12.5 Gbaud serial data communication

Abstract

Fully integrated SiGe BiCMOS transmit and receive PLLs for 8B/10B coded 10Gb/s serial links operate with excellent jitter characteristics. The transmit PLL (TxPLL) provides a 12.5GHz clock with 0.4ps rms jitter synthesized from a -195.3MHz reference. The receive PLL (RxPLL), which exhibits <0.56ps rms jitter generation, extracts a full rate clock and recovers data from a 12.5Gbis input bit stream. The RXPLL operates error-free when tested with a 14km optical link test bench. The power consumption of the TxPLL and RxPLL cores at 3.3V are 270mW and 330mW, respectively.

SiGe HBT BiCMOS for 2-160 Gb/s Next Generation Internet (NGI)

“…A multiple data rate CDR circuit is presented in [3], which detects incoming data rate and adjusts a PLL divider automatically. In [4], a 12.5Gb/s Tx/Rx set of PLLs are described using a 45GHz fT SiGe process. CDRs capable of 19GHz [5] using HEMTs with 50GHz fT have been reported as early as 1994.…”

The Impact of SiGe BiCMOS Technology on Microwave Circuits and Systems

“…The total chip area is 3. More recently, sub-picosecond-jitter transmit and receive PLL s for 12.5-Gb/s serial data transmission links have been developed using the same SiGe BiCMOS technology [22]. The power consumption of these fully-monolithic transmit and receive PLL cores at 3.3 V are 270 mW and 330 mW, respectively.…”

A 0.18‐μm SiGe BiCMOS HBT VCO using diode degeneration

“…This article proposes a differential VCO circuit using an nMOSFET cross‐coupled oscillator stacked in series with two hetero‐junction bipolar transistors (HBTs) configured as diodes. Figure 1 shows the schematics of two popular differential BJT LC VCOs [1, 2]. The cross‐coupled differential pair of bipolar transistors uses positive feedback to form a negative‐resistance cell that restores energy lost by the oscillator in each cycle.…”