Simulation of the influence of via sidewall tapering on step coverage of sputter-deposited barrier layers

166

The BOSCH etch process, which is commonly used in microelectromechanical system fabrication, has been extensively investigated in this work for implementation in through-silicon via (TSV) technology for 3D-microsystems packaging. The present work focuses on thermo-mechanical stresses caused by thermal loading due to post-TSV processes and their impact on the electrical performance of through-silicon copper interconnects. A test vehicle with deep silicon copper-plated comb structure was designed to study and evaluate different deep silicon via etch processes and its effect on the electrical leakage characteristics under various electrical and thermal stress conditions. It has been shown that the leakage current between the comb interconnect structures increases with an increase in sidewall roughness and that it can be significantly lowered by smoothening the sidewalls. It was also shown that by tailoring a non-BOSCH etch process with the normal BOSCH process, a similar leakage current reduction can be achieved. It was also shown through thermo-mechanical simulation studies that there is a clear correlation between high leakage current behavior due to non-uniform Ta barrier deposition over the rough sidewalls and the thermo-mechanical stress induced by post-TSV processes.

Section: Parameter-ramped Bosch Etch Processmentioning

confidence: 99%

A study of thermo-mechanical stress and its impact on through-silicon vias

Ranganathan

Prasad

Balasubramanian

et al. 2008

166

“…• is expected to be a good trade-off with respect to the seed layer deposition and top area opening [5,6].…”

Section: Introductionmentioning

confidence: 99%

“…However, the introduction of tapering slightly decreases the interconnection density due to the larger opening (undercut) of the vias. A typical slope angle between 80 • and 85 • is expected to be a good trade-off with respect to the seed layer deposition and top area opening [5,6].…”

Section: Introductionmentioning

confidence: 99%

Continuous deep reactive ion etching of tapered via holes for three-dimensional integration

Lamy

Roozeboom

et al. 2008

A continuous SF 6 /O 2 plasma process at room temperature has been used to etch tapered through-silicon vias using a DRIE-ICP tool. These features (10-100 μm in diameter) are aimed for applications in 3D integration and MEMS packaging. The effects of various process parameters such as O 2 flow rate, platen bias, pressure and substrate temperature on the via profile (depth, slope angle and aspect ratio) development are investigated. The etching mechanism was also studied and x-ray photoelectron spectroscopy (XPS) analysis reveals a SiO x passivation layer of the order of ∼2 nm on the via sidewall and a substantial temperature dependence. Both tapering and anisotropy of etching depend on this passivation layer formation. Finally, suitable tapered vias with an aspect ratio of ∼5 and a slope angle of ∼83• are obtained by properly balancing the etching regimes. In this condition, a maximum etch rate of 7 μm min −1 is achieved.

“…The biggest challenge in applying copper electroplating technology for TSV application lies in achieving a uniform sidewall deposition of the dielectric liner, copper diffusion barrier and copper seed layer, and finally a voidfree copper electrodeposition inside the TSV [6]. A preferred approach to overcoming these challenges is to form tapered or sloped TSV as it facilitates uniform sidewall deposition for dielectric, barrier and copper seed metallization [7,8]. Figure 3 illustrates how a tapered via structure can help in improving the step coverage of plasma deposited dielectric and barrier/seed metallization over high aspect ratio structures [9].…”

Section: Introductionmentioning

confidence: 99%

The development of a tapered silicon micro-micromachining process for 3D microsystems packaging

Ranganathan

Lee

Liao

et al. 2008

It has been shown that as the aspect ratio of through-silicon vias (TSV) increases, tapering of TSV structure greatly helps in achieving good sidewall coverage for dielectric, barrier and copper seed metal layers to eventually achieve a void-free copper via-filling by electroplating process. In the present work, a novel three-step tapered via etching process has been developed and demonstrated as a viable process for fabricating a void-free through-silicon copper interconnection structure. This paper discusses in great detail about the plasma etch mechanisms responsible for the step-by-step evolution of tapered silicon via the profile angle in the desirable range of 83-87 • . It is further shown that the above multi-step etch process enables the formation of void-free copper vias for via depths close to 300 μm.