Continuous deep reactive ion etching of tapered via holes for three-dimensional integration

Abstract

A continuous SF 6 /O 2 plasma process at room temperature has been used to etch tapered through-silicon vias using a DRIE-ICP tool. These features (10-100 μm in diameter) are aimed for applications in 3D integration and MEMS packaging. The effects of various process parameters such as O 2 flow rate, platen bias, pressure and substrate temperature on the via profile (depth, slope angle and aspect ratio) development are investigated. The etching mechanism was also studied and x-ray photoelectron spectroscopy (XPS) analysis reveals a SiO x passivation layer of the order of ∼2 nm on the via sidewall and a substantial temperature dependence. Both tapering and anisotropy of etching depend on this passivation layer formation. Finally, suitable tapered vias with an aspect ratio of ∼5 and a slope angle of ∼83• are obtained by properly balancing the etching regimes. In this condition, a maximum etch rate of 7 μm min −1 is achieved.

Inductively coupled plasma etching of tapered via in silicon for MEMS integration

“…Further increasing oxygen flow would significantly decrease selectivity to PR mask because it has to increase RF bias power at the same time. Key points, using SiF 6 -O 2 chemistry at room temperature, has been systematically discussed in Li's paper [7]. Decreasing the temperature enables an SF 6 -O 2 chemistry to form enough SiF x O y polymer during Si etching at a cryogenic temperatures.…”

“…Moreover the process may not be tolerated by unprotected device areas on the surface. Recently, it has been shown that a SF 6 -O 2 chemistry may be used to realize an 80°via profile, but a 70°pro-file has proven difficult to achieve [6,7]. An anisotropic wet etch that is selective to the <1 1 1> planes, such as KOH, EDP or TMAH, may achieve a tapered profile but at a fixed angle 54.74°for <1 0 0> silicon wafers [8].…”

Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications

“…In the last decades through wafer electrical connections became a more and more important issue for different applications, mainly for 3D integration of MEMS (MicroElectro-Mechanical systems), like wafer-level packaging or vertical connections in stacked wafers devices (Li et al 2007(Li et al , 2008. Manufacturing involve two stages: through wafer via holes manufacturing and holes filling with a conductive layer.…”

“…DRIE processes also have other advantages over competing technologies. Depending on the plasma recipe used, it is possible to obtain different isotropy during the processes-this can be used to obtain vertical walls with a high aspect ratio, up to 20:1 (Wolf et al 2008), tapered walls (Li et al 2008) or even isotropic etching (Larsen et al 2005). Moreover, due to the possibility of changing the isotropy during the etching process by modifying the plasma composition, it is possible to manufacture structures which cannot be obtained using only isotropic or anisotropic processes (Gassend et al 2010).…”

“…The most common way to deposit these layers is Physical Vapor Deposition (PVD), but this technique have a limited step coverage, being severely restricted for high aspect ratio via holes. Another solution to obtain a more conformal deposition of barrier and seed layers is to use tapered walls (Li et al 2008).…”