Simulation and design of a germanium L-shaped impact-ionization MOS transistor

Abstract

This paper reports a novel L-shaped impact-ionization MOS (LI-MOS) transistor structure that achieves a subthreshold swing of well below 60 mV/decade at room temperature and operates at a low supply voltage. The device features an L-shaped or an elevated impact-ionization region (I-region), which displaces the hot carrier activity away from the gate dielectric region to improve hot carrier reliability and V T stability problems. Germanium, which has a lower bandgap and impact-ionization threshold energy lower than silicon, is chosen as the material of choice for the LI-MOS transistor structure. Device physics and design principles for the LI-MOS transistor are detailed through extensive two-dimensional device simulations. The LI-MOS transistor exhibits excellent scalability, making it suitable for augmenting the performance of standard CMOS transistors in future technology generations.

Bipolar effects in unipolar junctionless transistors

“…This positive feedback mechanism actuates the parasitic "bipolar" effect in parallel, resulting in the sharp increase of drain current. [9][10][11][12][13][14][15][16][17][18][19] In the reverse sweep mode, i.e., In order to understand hysteresis effect in JNL devices, potential distribution, electron, and hole concentration, along a cut-line (shown in Fig. 3(a)) from…”

A Novel Enhanced Electric-Field Impact-Ionization MOS Transistor

“…Previous experimental results [3] have proved the validity of the local-field model. Since the dimensions used (L G , L IN , and L J ) are well above the threshold value (∼5 nm), below which the quantum effects become important [15], this model is reasonably accurate in our case. To correctly model the transport across the abrupt heterojunction between M-1 and M-2, both the thermionic emission and tunneling have been taken into account.…”

A Short Review on Deep-Sub-Voltage Nanoelectronics and Related Technologies

“…For example, in the RFID sector, the reservoir capacitor of the power unit in modern IC takes approximately 1/4 of the area, therefore S ≈ 0.25 according to Eq. (9). The prognosis of Ref.…”

“…8 The CMOS will not be planar beyond 22-nm node where FETs overcome such challenges as electrostatic control of the channel potential and suppression of leakage current between transistor source and drain in short channels. 9 A nonplanar tri-gate would be suited to such FET. 10 Projected devices with typical 16 nm half-pitch will be achieved around 2018.…”

“…Critical problem is a sub-voltage nanodevice that changes a current to several orders of magnitude at the 60 mV swing. 9 Reducing the energy consumption per 1 bit processing (ε) and supply voltage (V dd ) has been a major trend in micro-and nanoelectronics for a long period of time. At present, high-performance processors are becoming sub-voltage.…”