Silicon nanowires – a versatile technology platform

Mikolajick, Thomas; Heinzig, André; Trommer, Jens; Pregl, Sebastian; Grube, Matthias; Cuniberti, Gianaurelio; Weber, Walter M.

doi:10.1002/pssr.201307247

Cited by 63 publications

(36 citation statements)

References 46 publications

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“…13,14 To the best of our knowledge, this is the first proof of concept demonstrating a novel electrostatically doped, planar FET with an asymmetric dual-gate configuration which involves a combination of SBFET and JLFET properties for high temperature applications. * Electrochemical Society Active Member.…”

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confidence: 99%

“…12 Until now, all ambipolar devices using a separate gate to control the current flow between source and drain involve nanowire structures as, for example, silicon nanowires or carbon nanotubes. 13,14 To the best of our knowledge, this is the first proof of concept demonstrating a novel electrostatically doped, planar FET with an asymmetric dual-gate configuration which involves a combination of SBFET and JLFET properties for high temperature applications. * Electrochemical Society Active Member.…”

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confidence: 99%

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Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

Krauss

Wessely

Schwalke

2015

ECS J. Solid State Sci. Technol.

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In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device. The dominating leakage path for OFF-state currents in today's downscaled MOSFET devices originate from PN-junction and bulk leakage.1,2 These leakage currents increase severely with temperature. SOI technologies can significantly reduce bulk leakage currents. However, junction leakage because of reversed bias PN-junctions is still present in SOI MOSFETs.2 Therefore, our device concept replaces conventional S/D PN-junctions with Schottky barrier contacts in a virtually dopant-free CMOS environment. Many groups have demonstrated the advantages of SBFET devices like low S/D resistance as well as abrupt junctions enabling further scaling and suppression of parasitic bipolar behavior.4,5 Furthermore, JLFET demonstrating high temperature robustness have been reported. [6][7][8] We have combined the advantages of the SBFET and JLFET concepts on SOI in a novel asymmetric dual gate but single channel device. This combination improves the high temperature robustness as reported recently for our SiNW FETs.9,10 For the first time, we have successfully extended this 3D-SiNW concept to planar, non-nanowire device structures.We found that the combination of an ambipolar electrostatic doping back-gate (BG) in addition to an electrically separated current flow control front-gate (FG) in a single device results in a superior on-tooff current ratio and leakage suppression at high temperatures. The BG transistor as a SBFET shows an ambipolar behavior similar to the SBFET reported in.11 On the other hand, the unipolar FG transistor resembles the behavior of a JLFET as reported in Ref. 8. Furthermore, as no conventional impurity doping process is required, the device does not suffer from dopant dependent reduction of carrier mobility or statistic dopant fluctuation and resulting threshold voltage variation following the argumentation of 6 for JLFET devices. In addition, the degree of freedom to instantly select n-and ptype behavior via an ordinary electrical signal of appropriate polarity on the BG allows designing reconfigurable circuits with increased functionality.12 Until now, all ambipolar devices using a separate gate to control the current flow between source and drain involve nanowire structures as, for example, silicon nanowires or carbon nanotubes....

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confidence: 99%

mentioning

confidence: 99%

Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

Krauss

Wessely

Schwalke

2015

ECS J. Solid State Sci. Technol.

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“…Figure 1.4 shows examples of nanowires created by both techniques. [1] According to the above-described procedures the bottom-up fabrication will lead to a vertical arrangement of nanowires and the top-down arrangement will lead to a horizontal arrangement of nanowires. If horizontal nanowires have to be fabricated by the bottom-up technique, the alignment is very critical.…”

Section: Fabrication Techniques For Silicon Nanowiresmentioning

confidence: 99%

“…The very small diameter results in a large surface to volume ratio. This can be exploited in many ways in electronic devices [1]. When a gate is wrapped around the nanowire, the optimum control of the nanowire potential by the gate potential is ensured.…”

Section: Introductionmentioning

confidence: 99%

Silicon Nanowires: Fabrication and Applications

Mikolajick

Weber

2015

NanoScience and Technology

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Due to the high surface to volume silicon ratio and unique quasi onedimensional electronic structure, silicon nanowire based devices have properties that can outperform their traditional counterparts in many ways. To fabricate silicon nanowires, in principle there are a variety of different approaches. These can be classified into top-down and bottom-up methods. The choice of fabrication method is strongly linked to the target application. From an application point of view, electron devices based on silicon nanowires are a natural extension of the downscaling of a silicon metal insulator semiconductor transistor. However, the unique properties also allow implementing new device concepts like the junctionless transistor and new functionalities like reconfigurability on the device level. Sensor devices may benefit from the high surface to volume ratio leading to a very high sensitivity of the device. Also, solar cells and anodes in Li-ion batteries can be improved by exploiting the quasi one-dimensionality. This chapter will give a review on the state-of-the-art of silicon nanowire fabrication and their application in different types of devices.

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“…Two reviews address nanowire growth [1,2], three various properties of nanowires [3][4][5], and five reviews describe applications ranging from thermoelectrics [6] to sensing [7], electronics [8], optoelectronics [9], and photovoltaics [10]. The letters have been grouped according to the following subjects: growth, microstructure, spectroscopic investigations, doping and impurities, transport, and applications.…”

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Focus on Semiconductor Nanowires

Jagadish¹,

Geelhaar²,

Gradečak³

2013

Physica Rapid Research Ltrs

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Semiconductor nanowires are structures that are characterized by their high aspect ratio and a diameter that typically does not exceed 100 nm. The nanoscale size and the quasi one‐dimensional shape offer unique opportunities to control properties of semiconductors such as density of states, transport of electrons, and interaction with photons. Thus, these objects are considered as building blocks for the next generation of electronics, photonics, energy, sensing, and biomedical applications. Another important feature of nanowires is the possibility to grow hetero‐structures of materials with large lattice and thermal mismatch without creating dislocations. This advantage over planar films provides an unprecedented flexibility to create a broad range of structures with a combination of different materials that may lead to the observation of exciting physical phenomena or novel functionalities for applications. In particular, nanowires may pave the way for the integration of microelectronic devices on silicon with optoelectronic and photonic devices based on compound semiconductors. Over the past decade, research on semiconductor nanowires has become one of the most active fields in nanoscience and technology, and the number of groups working on this topic is still increasing. One particularly exciting aspect of this research field is its interdisciplinary nature that brings together scientists trained in physics, chemistry, materials science, electrical engineering, biology, and medicine. The purpose of this Focus Issue is to provide both an overview of the field in the form of Reviews but also a snapshot of ongoing activities in the form of Letters. The idea for this Focus Issue was born during ‘Nanowires 2012’, a workshop on the physics, chemistry and applications of nanowires that took place in Berlin in September 2012. The guest editors and the editor‐in‐chief of pss (RRL) met on this occasion, and discussed the topics to be covered and structure of the special issue. Both the ten Review@RRL articles and 21 Letters in this Focus Issue cover a wide scope of topics, methods, and materials. Two reviews address nano‐wire growth [1, 2], three various properties of nano‐wires [3–5], and five reviews describe applications ranging from thermoelectrics [6] to sensing [7], electronics [8], optoelectronics [9], and photovoltaics [10]. The letters have been grouped according to the following subjects: growth, microstructure, spectroscopic investigations, doping and impurities, transport, and applications. Essentially the entire range of inorganic semiconducting materials is covered in this Focus Issue, from Si and Ge, both narrow and wide bandgap II–VI, III–V, and IV–VI compound semiconductors to semiconducting oxides. The studies are based on experimental techniques including various growth methods, microscopy, diffraction, spectroscopy, and electrical characterization but also on theoretical approaches as diverse as density functional theory and self‐consistent solutions of the Schrödinger–Poisson equations. We...

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Silicon nanowires – a versatile technology platform

Cited by 63 publications

References 46 publications

Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

Silicon Nanowires: Fabrication and Applications

Focus on Semiconductor Nanowires

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