Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

Mertens, Hans; Ritzenthaler, R.; Arimura, Hiroaki; Franco, J.; Sebaai, Farid; Hikavyy, Andriy; Pawlak, B. J.; Machkaoutsan, V.; Devriendt, K.; Tsvetanova, Diana; Milenin, Alexey; Witters, L.; Dangol, A.; Vancoille, E.; Bender, Hugo; Badaroglu, Mustafa; Holsteyns, Frank; Barla, K.; Mocuta, D.; Horiguchi, N.; Thean, A.

doi:10.1109/vlsit.2015.7223654

Cited by 45 publications

(26 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Where ψms is the work function difference between metal and semiconductor, ψm' and χ' are the modified metal work function and electron affinity which are modified to the oxide conduction band, and the potential ψ fp is the difference between EFi and EF. Since the identical TiN gate metal and the high-k oxide layer HZO are used for the two different devices, the energy band gap difference between Si and Si0.8Ge0.2 is about 0.14eV, and the electron affinity difference is negligible, from the equation (1) and (2), it is only 0.07V VFB difference which attribute to different materials used for two devices. As a result, the 0.3V VTH shift for the Si0.8Ge0.2 UT-FinFET is mostly due to the Quantum confinement effect (QCE) which is invoked as the fin channel has only 5 nm width.…”

Section: Resultsmentioning

confidence: 99%

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio

Sun

Tsai

Yan

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

We successfully fabricate the Si0.8Ge0.2 channel fin field-effect-transistor (FinFET) with 5 nm ultra-thin fin width and high aspect ratio (~10×) on silicon-on-insulator (SOI) substrate by simple two-step dry etching. In comparison of the conventional Si FinFET, our proposed SiGe ultra-thin FinFETs (Si0.8Ge0.2 UT-FinFET) at VD = 0.75 V & VG = 1.5 V shows higher ON-state current (1 mA/fin), even achieve lower OFF-state current (0.2 nA/fin) and steep subthreshold slope (SS) of 76 mV/decade, which is owing to the better gate control given by the ultra-thin fin channel. In addition, this work also exhibits the suppression of short channel effect (SCE) with very small drain induced barrier-lowering (DIBL) of 4 mV/V.

show abstract

Section: Resultsmentioning

confidence: 99%

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio

Sun

Tsai

Yan

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…As discussed earlier, achieving ideal sub-threshold characteristics is challenging for HGC SiGe devices using a Si-cap-free surface passivation process, especially in an RMG flow. Best values reported so far for HGC SiGe and Ge FinFETs are in the range of 80-100mV/dec [8][9][10][11]. Figure 11 shows median long-channel sub-threshold slope (SS) (Ldes=1µm) of our HGC SiGe FinFETs with an optimized gate first process, a standard RMG baseline and an optimized RMG process.…”

Section: Electrical Results and Discussionmentioning

confidence: 99%

Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations

Hashemi¹,

Balakrishnan²,

Ando³

et al. 2016

ECS Trans.

View full text Add to dashboard Cite

High Ge content SiGe FETs have recently drawn significant attention as a candidate for p-MOSFETs due to their enhanced transport and reliability properties and compatibility with bulk or SOI substrates. In addition, compared to strained pure germanium, they can offer reduced off-state tunneling leakage due to their relatively larger bandgap. Utilization of high Ge content SiGe in a FinFET architecture by direct epitaxial growth is quite challenging due to epitaxial critical thickness constraints, resulting in high levels of defectivity which may be detrimental to the device functionality and performance. In this paper, we review our recent progress on high Ge content SiGe FinFETs with Ge content over 60%. In particular, gate stack, passivation and equivalent oxide thickness scaling are major factors in achieving high quality devices based on high Ge content SiGe. We present our results based on a Si-cap-free FinFET surface passivation to achieve excellent sub-threshold swings for both gate first and replacement high-K and metal gate integration flows. In addition, various device aspects such as transport and mobility, S/D and junction, off-state drain leakage current and short channel performance are discussed.

show abstract

“…Also, it prevents the boron from diffusing into high-k because the diffusion into hafnium oxide (HfO 2 ) occurs much slower than SiO 2 [ 232 , 233 ]. The RMG process still will work well for the 7 nm and 5 nm technology node with SiGe nanowires through selectively removing the Si sacrificial layer from the SiGe channel material [ 234 ]. Meanwhile, for technology nodes 3 nm and beyond, the sacrificial material is SiGe and will be selectively removed from Ge channel [ 235 , 236 , 237 ].…”

Section: Wet Cleaningmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

View full text Add to dashboard Cite

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

show abstract

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

Cited by 45 publications

References 4 publications

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio

Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations

State of the Art and Future Perspectives in Advanced CMOS Technology

Contact Info

Product

Resources

About

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

Cited by 45 publications

References 4 publications

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio

Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations

State of the Art and Future Perspectives in Advanced CMOS Technology

Contact Info

Product

Resources

About

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio