Series Resistance Extraction in Poly-Si TFTs With Channel Length and Mobility Variations

Zhou, Yan; Wang, Mingxiang; Wong, Man

doi:10.1109/led.2011.2142391

Cited by 6 publications

(3 citation statements)

References 17 publications

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“…It is clearly seen that the I OFF of studied poly-Si TFTs is significantly reduced by including LDD structures that effectively reduce the E-field strength near the drain junction. 11,12,20,21) As expected, the I ON of Conv.-LDD TFTs is lower than that of the Conv. TFTs due to the high-resistive LDDs.…”

Section: Resultssupporting

confidence: 76%

“…Besides, the high E-field near the drain junction would also give rise to hot carrier degradation. [17][18][19] Lightly-doped drain (LDD) structures 11,12,20,21) can be implemented to address the high peak E-field issues encountered by conventional poly-Si TFTs. However, additional lithographic and sidewall-spacer steps are needed for forming the LDD structures, complicating the device fabrication.…”

Section: Introductionmentioning

confidence: 99%

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Fabrication and characterization of T-gate polysilicon thin-film transistors with lightly-doped drain

Lee

Chen

Huang

et al. 2022

Jpn. J. Appl. Phys.

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We report detailed fabrication and characterization of poly-Si thin-film transistors (TFTs) with T-shaped gate (T-gate) and lightly-doped drain (LDD) structures. The formation of the LDD underneath the wings of a T-gate primarily relies on the shadowing of implanted dopants during the implantation of source and drain. Therefore, the fabrication of LDD structures in our proposed T-gate poly-Si TFTs can save a number of process steps as compared to conventional poly-Si TFTs with LDD structures. Our fabricated T-gated poly-Si TFTs with LDD structures not only exhibit suppressed off-state leakage current but also show a significant improvement in on-state current as compared to that of conventional poly-Si TFTs with the same top-gate dimension.

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Section: Resultssupporting

confidence: 76%

Section: Introductionmentioning

confidence: 99%

Fabrication and characterization of T-gate polysilicon thin-film transistors with lightly-doped drain

Lee

Chen

Huang

et al. 2022

Jpn. J. Appl. Phys.

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“…[1][2][3][4][5] In the (Ultra-Large-Scale-Integration) ULSI or beyond technologies, polysilicon resistors have been widely used throughout the semiconductor industry for a variety of applications especially employed in Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits as a precise analog resistor element for a variety of applications, such as DAC (digital resistor give the solution of the linearity and Rs concerns to analog converter) in analogue circuits. [6][7][8][9][10][11][12][13][14] Conventionally the polysilicon resistance can be adjusted by ion implantation and post annealing process. 15,16 For the self-aligned implantation process, the dosage changes which are always utilized to adjust the resistance are feasible to induce the MOS characteristics changes, especially in the submicron process whose short-channel effects (SCE) are much more sensitive to the implant dosage.…”

mentioning

confidence: 99%

Thermal Method to Reduce the Polysilicon Resistance for Deep Submicron Integration Process

Liu

et al. 2016

ECS J. Solid State Sci. Technol.

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In this paper, a new annealing process to reduce polysilicon resistance without implant dosage adjustment has been proposed. With increasing the annealing temperatures, polysilicon grain size increases and causes the polysilicon resistance reduction. After annealing in inert gas ambient at 950°C for 5 min, the polysilicon resistance can be obviously reduced more than 7.7%, comparing to the 800°C for 5 min annealing process. And the threshold voltage and saturation current characteristics of submicron MOS device can be maintained almost same as before, due to the minor doping profile variations. Therefore, this new annealing process without device performance variations can be a candidate to reduce the polysilicon resistance applied to deep submicron integration circuit process.

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In-depth analysis of electrical characteristics for polycrystalline silicon vertical thin film transistors

Zhang

Jacques

Rogel

et al. 2021

Solid-State Electronics

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A polycrystalline silicon vertical thin film transistor (VTFT) is fabricated, and the electrical parameters are extracted and compared with the typical lateral thin film transistor (LTFT). The similar subthreshold slope and the distinct field effect mobility is verified by the DOS calculation in the deep and shallow trap regions, respectively, and in this article, it is used to compare with the grain boundary trap density at a lower V ds =10 mV that eliminates the velocity saturation effect. The accurate threshold voltage is also calculated by a systematic model including the grain boundary barrier modulation effect. A pseudo-subthreshold region is demonstrated, and the threshold voltage exactly corresponds to the 3kT point of the grain boundary barrier. The low field effect mobility of VTFT is mainly due to the small grain size and also slightly affected by the parasitic resistance, which can be improved by optimizing the processing conditions, especially by improving the sidewalls smoothness and the active layer quality.

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Series Resistance Extraction in Poly-Si TFTs With Channel Length and Mobility Variations

Cited by 6 publications

References 17 publications

Fabrication and characterization of T-gate polysilicon thin-film transistors with lightly-doped drain

Fabrication and characterization of T-gate polysilicon thin-film transistors with lightly-doped drain

Thermal Method to Reduce the Polysilicon Resistance for Deep Submicron Integration Process

In-depth analysis of electrical characteristics for polycrystalline silicon vertical thin film transistors

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