In this paper, a new annealing process to reduce polysilicon resistance without implant dosage adjustment has been proposed. With increasing the annealing temperatures, polysilicon grain size increases and causes the polysilicon resistance reduction. After annealing in inert gas ambient at 950°C for 5 min, the polysilicon resistance can be obviously reduced more than 7.7%, comparing to the 800°C for 5 min annealing process. And the threshold voltage and saturation current characteristics of submicron MOS device can be maintained almost same as before, due to the minor doping profile variations. Therefore, this new annealing process without device performance variations can be a candidate to reduce the polysilicon resistance applied to deep submicron integration circuit process.
In the ultra-large-scale integration (ULSI) technologies, polysilicon resistors are usually employed in the integrated circuits as a precise analog resistor element for a variety of applications, such as DAC (digital resistor give the solution of the linearity and Rs concerns to analog converter) in analogue circuits [1-3]. Conventionally the polysilicon resistance can be adjusted by ion implantation and post annealing process [4]. For the self-aligned implantation process, the dosage changes which are always utilized to adjust the resistance are feasible to induce the MOS characteristics changes, especially in the submicron process whose short-channel effects (SCE) are much more sensitive to the dosages [5]. In this work, we propose a new inner anneal process in N2ambient after polysilicon re-oxidation to reduce the polysilicon resistance by changing the polysilicon grain size. The test patterns are manufactured on 300mm-diameter wafer by 65-nm 1-poly 7-metal standard CMOS technology. After polysilicon re-oxidation to form oxide film on polysilicon surface, the wafers are annealed at 800oC, 900oC, 950oC and 1000oC in N2ambient, respectively. Fig. 1 shows the process flow and annealing process steps in the flow. After anneal, the polysilicon grain size is measured by X-ray powder diffraction (XRD). And the electric characteristics for NMOS, PMOS and polysilicon resistance are tested. Fig. 2 shows the poly resistance reduction proportion and poly grain size after anneal at 800oC, 900oC, and 1000oC for 5min, and 950oC for 20min in N2 ambient, respectively. Only after annealing at 950oC or above for 5min, the resistance can be obviously reduced, due to the poly grain size increasing. Fig. 3 shows threshold voltages (Vt) variation proportions of NMOS and PMOS owning gate length of 65nm and width 0.12µm after utilizing annealing process at different temperatures. PMOS is more sensitive to the anneal process than NMOS. But after anneal at 950oC or below, the threshold variation for both NMOS and PMOS is less than 5%, which is acceptable for the integration process manufacturing. A new anneal process at N2 ambient to adjust the polysilicon resistance has been proposed. It has been verified that utilizing anneal process at 950oC or below, the 65nm MOS performances can be maintained almost same as before. Consequently, it is considered that the anneal method can be to be applied to the deep submicron integration process. References [1] C. D. Parikh, and R. M. Patrikar, Solid-state Electronics, 43, 683 (1999). [2] R. Murii, and M. J. Deen,, IEEE Trans. Electron Devices, 49, 187 (2002). [3] C. Uang, H. Chuang, S. Tsai, K. Thei, P. Lai, S. Fu, Y. Tsai, W. Liu, IWJT, 293 (2004). [4] S. Gupta, J. Electrochem. Soc. 149, G271 (2002). [5] R. H. Dennard, F. J. Gasensslen, H. M. Yu, V. L. Rideout, E. Bassous, A. R. Leblanc, Solid-state Circuits Soc Mag. IEEE, 87, 668 (1999). Figure 1
The slopes reinforced by anti-slide piles were simulated in this paper. The setting position, pile spacing and anchorage depth of integrated piles were discussed with strength reduction method. The results show that the pile position should depart slope into two stages, and the further strain would be limited. When the spacing of the anti-slide piles is 2-3 times of pile diameter, it has a soil arching effect to wedge the soil. The anchorage depth can affect the form of the potential sliding surface. Three kinds of defective piles were studied to research deformation of slope reinforced by defective piles. The defective piles were namely expanded pile, necking pile and segregationpile. The equivalent plastic strain zone was used to judge the slope failure, and then the stability and deformation process of the three-dimensional slope were simulated. By comparing the plastic strain, safety coefficient curve and pile-soil stress curve, between the defective pile and integrated pile, the progressive failure process of the reinforced slope was analyzed, including the formation process of the macroscopic shear zone.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.