Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors

Yang, Xuebei; Fiori, Gianluca; Iannaccone, Giuseppe; Mohanram, Kartik

doi:10.1145/1785481.1785538

Cited by 5 publications

(2 citation statements)

References 26 publications

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“…The interface between the metal drain/source and the GNR channel results in a SB at the graphene-metal junction. SB-GNRFETs have an ambipolar I -V curve with minimum current at V GS = 1/2V DS [12], [13].…”

Section: Sb-gnrfet Modelingmentioning

confidence: 99%

“…Numerical simulations based on nonequilibrium Green's function formalism have been implemented in the 3-D device simulator NanoTCAD ViDES in [9]- [11]. Nonclosed-form analytical models that describe SB-GNRFETs are presented in [12] and [13]. In terms of high-level simulations, a circuit simulation framework of SB-GNRFETs based on lookup tables is presented in [14].…”

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confidence: 99%

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Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis

Gholipour

Chen

Sangai

et al. 2016

IEEE Trans. VLSI Syst.

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This paper presents an accurate analytical compact model for Schottky-barrier-type graphene nanoribbon field-effect transistors (SB-GNRFETs). This is a physics-based analytical model for the current-voltage (I-V ) characteristics of SB-GNRFETs. The proposed model considers various design parameters and process variation effects, including graphenespecific line-edge roughness, which allows thorough exploration and evaluation of SB-GNRFET circuits. We develop accurate approximations of SB tunneling, channel charge, and current, which provide accurate results while maintaining model compactness. We evaluate the effect of design parameters and process variations on the performance of SB-GNRFETs. We also compare circuit-level performance of SB-GNRFETs with multigate (MG) Si-CMOS (e.g., FinFETs). Our circuit simulations indicate that SB-GNRFET has an energy-delay product (EDP) advantage over Si-CMOS, although GNR-specific process variation, especially the line-edge roughness, would significantly downgrade such an advantage; the EDP of the ideal SB-GNRFET (assuming no process variation) is ∼2.5% of that of Si-CMOS, while the EDP of the nonideal case with process variation is ∼68% of that of Si-CMOS. Finally, we study technology scaling with SB-GNRFET and MG Si-CMOS. We show that the EDP of ideal (nonideal) SB-GNRFET is ∼0.88% (54%) EDP of that of Si-CMOS as the technology nodes scale down to 7 nm.Index Terms-Graphene nanoribbon field-effect transistor (GNRFET), nanoelectronics, Schottky barrier (SB), SPICE model.

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Section: Sb-gnrfet Modelingmentioning

confidence: 99%

mentioning

confidence: 99%