Self-heating effect in FinFETs and its impact on devices reliability characterization

Liu, S. E.; Wang, J. S.; Lu, Yi-Chun; Huang, Danqiong; Huang, Chia-En; Hsieh, Wen-Wen; Lee, J. H.; Tsai, Y. S.; Shih, J.R.; Lee, Y.-H; Wu, Kaijie

doi:10.1109/irps.2014.6860642

Cited by 95 publications

(23 citation statements)

References 8 publications

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“…Some trends for a single transistor under different biases can be concluded: (1) as the frequency decreases, the TVS increases; (2) PRBS stress suffers more severe HCI than AC stress at the same frequency [26]. The above-mentioned conclusion is also validated by experiment data [3,15,42,43,60]. Based on the temperature response, the TVS under different waveforms and frequencies is further captured as shown in Figure 4a,c [26], respectively.…”

Section: Simulation Resultsmentioning

confidence: 57%

“…Furthermore, low thermal conductivity of the more confined thin films in silicon-on-insulator (SOI) MOSFET and FinFET leads to more severe SHEs [54][55][56][57]. As a result, the temperature in nanoscale transistors increases significantly [58][59][60][61]. Severe SHE further deteriorates HCI reliability for nanoscale transistors, which is a big concern in modern nanoscale transistors [3,41,42,50,62].…”

Section: Introductionmentioning

confidence: 99%

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Hot Carrier Injection Reliability in Nanoscale Field Effect Transistors: Modeling and Simulation Methods

Wang

Yang³

et al. 2022

Electronics

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Hot carrier injection (HCI) can generate interface traps or oxide traps mainly by dissociating the Si-H or Si-O bond, thus affecting device performances such as threshold voltage and saturation current. It is one of the most significant reliability issues for devices and circuits. Particularly, the increase in heat generation per unit volume due to high integration density of advanced integrated circuits leads to a severe self-heating effect (SHE) of nanoscale field effect transistors (FETs), and low thermal conductivity of materials in nanoscale FETs further aggravates the SHE. High temperature improves the HCI reliability in the conventional MOSFET with long channels in which the energy of carriers can be relaxed. However, high temperature due to severe SHE deteriorates HCI reliability in nanoscale FETs, which is a big concern in device and circuit design. In this paper, the modeling and simulation methods of HCI in FETs are reviewed. Particularly, some recently proposed HCI models with consideration of the SHE are reviewed and discussed in detail.

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Section: Simulation Resultsmentioning

confidence: 57%

Section: Introductionmentioning

confidence: 99%

Hot Carrier Injection Reliability in Nanoscale Field Effect Transistors: Modeling and Simulation Methods

Wang

Yang³

et al. 2022

Electronics

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“…Due to this effect are either short or open of the signal line or power line takes place. FinFETs have a short channel control and switching characteristics [6] and the device scaling can be extended to nano-scale regime. The heat dissipation in FinFET is poor because of phonon boundary scattering that may cause Self-Heating Effect in circuit operations [7].…”

Section: International Journal Of Engineering Research In Electronics...mentioning

confidence: 99%

Untitled

2022

IJERECE

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VLSI industry has been rapidly growing where multiple processors can be implemented on a single chip. In physical design of a chip main factors to be considered are timing closure, congestion, and power. Compare to 180nm and 90nm designs were not much complicated due to less transistor density as going to lower technology nodes chip size, area, length will decrease that impact on packaging and cooling issues, so it is necessary to estimate the power at the early stage of design. Power analysis is done immediately after placement and routing stage of the chip. Power analysis can be performed in two methods one is flat method and other is hierarchical method. In flat method of analysis, the data of both top level and block level is given as input data to calculate the results whereas in hierarchical method of analysis the Power Grid View (PGV) of hierarchical block is designed which is then given as input. In hierarchical runs the sub-blocks are black boxed. The simulation is carried out using the Voltus IC Integrity Solution tool from cadence for a chip designed in 16nmFinFET technology. The results obtained from the flat method of analysis takes 2X the runtime compared to hierarchical method which would be unfavorable for very much larger circuits. The IR drop in VDD and VSS are 11.69 mW and 11.02mW respectively in flat method and 12.32 mW and 13.26 mW for VDD and VSS in hierarchical method of analysis. The accuracy is more obtained in flat run due to its transparency in logic functions.

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“…While the BTI generates the electrical field perpendicular to the channel, the hot carrier injection (HCI) combines horizontal and perpendicular electric field to the channel. The HCI accompanied with the self-heating effect exhibits more degradation for FinFETs than what is expected [25][26][27]. However, the interface state generation and oxide trap can be passivated (recovered) by bond formation with hydrogen atoms [26,28].…”

Section: Introductionmentioning

confidence: 96%

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Chang¹,

Li²,

Hsu³

et al. 2021

IEEE Open J. Nanotechnol.

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High-k metal gate technology improves the performance and reduces the gate leakage current of metal-oxide-semiconductor field-effect transistors (MOSFETs). This study investigated four different work function metal (WFM) stacks in the gate of fin field-effect transistors (FinFETs) on the same substrate. These devices not only successfully produced distinct levels of threshold voltages (|V t |) but also converted n-to p-type features merely by adding p-type WFM in the gate of the MOSFETs. All of the devices satisfied short-channel effects with shrinking channel length. The gate-to-body electric field induced drain leakage due to the nature of bulk FinFETs. However, the n-and p-type gate stacks presented different gate current leakage. For reliability, hot carrier injection (HCI) could have a higher reliability impact than the negative-bias temperature instability (NBTI) for p-MOSFET, although the stress voltage of HCI was roughly half that of the NBTI test. This multi-threshold voltage tuning allows designers to design CMOS and choose the trade-off between low power consumption and high performance on the same platform.

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Self-heating effect in FinFETs and its impact on devices reliability characterization

Cited by 95 publications

References 8 publications

Hot Carrier Injection Reliability in Nanoscale Field Effect Transistors: Modeling and Simulation Methods

Hot Carrier Injection Reliability in Nanoscale Field Effect Transistors: Modeling and Simulation Methods

Untitled

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

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