Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

Hill, Richard J.; Park, C.; Barnett, Joel; Price, Jimmy; Huang, Jen-Fa; Goel, Nilesh; Loh, Wei‐Yip; Oh, Jungkeun; Smith, Casey; Kirsch, P. D.; Majhi, P.; Jammy, R.

doi:10.1109/iedm.2010.5703307

Cited by 45 publications

(34 citation statements)

References 4 publications

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“…High mobility III-V FET devices show promising features for integration in digital logic [1][2][3][4][5][6][7][8]. It is predicted that the inclusion of these material on a Si platform will enable the continuation of transistor scaling, primarily by delivering an increased drive current at low supply voltage.…”

Section: Introductionmentioning

confidence: 99%

High transconductance self-aligned gate-last surface channel In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFET

Egard

Ohlsson

Borg

et al. 2011

2011 International Electron Devices Meeting

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AbstractsIn this paper we present a 55 nm gate length Ino.5 3 Gao.4 7 As MOSFET with extrinsic transconductance of 1.9 mS/llm and on-resistance of 199 Ql1m. The self-aligned MOSFET is formed using metalorganic chemical vapor deposition regrowth of highly doped source and drain access regions.The fabricated 140 nm gate length devices shows a low subthreshold swing of 79 m V /decade, which is attributed to the described low temperature gate-last process scheme.

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Section: Introductionmentioning

confidence: 99%

High transconductance self-aligned gate-last surface channel In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFET

Egard

Ohlsson

Borg

et al. 2011

2011 International Electron Devices Meeting

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“…[1][2][3][4][5][6][7][8][9][10][11][12] High performance III-V MOSFETs require low source and drain (S/D) series resistance R S/D , which includes metal-semiconductor contact resistance. [13][14][15][16][17][18] To achieve low R S/D in III-V FETs, S/D engineering such as selective growth of in situ doped S/D materials [19][20][21] and self-aligned contacts have been employed.…”

mentioning

confidence: 99%

Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization

Zhang

Guo

Lin

et al. 2011

Electrochem. Solid-State Lett.

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In 0.7 Ga 0.3 As channel n-MOSFETs (metal-oxide-semiconductor field-effect transistors) with Si-doped S/D and self-aligned NiInGaAs contact were demonstrated for the first time. The salicide-like metallization process employed a direct reaction between Ni and Si-doped InGaAs, followed by the removal of the unreacted Ni. As compared with n-MOSFETs with metallic Ni-InGaAs S/D (i.e. no Si doping in S/D), n-MOSFETs with Ni-InGaAs contact formed on Si-doped S/D show significantly improved OFFstate current I OFF in the linear and saturation regions.III-V materials such as Indium Gallium Arsenide (InGaAs) and Indium Arsenide (InAs) have significantly higher electron mobility than Silicon (Si) and are attractive for future high speed low power logic applications. 1-12 High performance III-V MOSFETs require low source and drain (S/D) series resistance R S/D , which includes metal-semiconductor contact resistance. 13-18 To achieve low R S/D in III-V FETs, S/D engineering such as selective growth of in situ doped S/D materials 19-21 and self-aligned contacts have been employed. [17][18]21,22 Metallic S/D is another attractive option 23-26 and should preferably be self-aligned to the gate stack. InGaAs channel n-MOSFETs with self-aligned metallic Ni-InGaAs S/D have been demonstrated recently. 25,26 However, the n-MOSFETs with metallic S/D suffer from high leakage current at metal/semiconductor junctions in S/D regions, leading to high drain to source and drain to body leakage current. Low drain junction leakage is needed to achieve low standby power consumption.In this work, In 0.7 Ga 0.3 As channel n-MOSFETs with Si-doped S/ D and self-aligned Ni-InGaAs contact were demonstrated for the first time. The spacer-less metallization process is similar to salicidation and drives the diffusion of Ni into InGaAs for reaction to form a conductive material. S/D implant (Si) and dopant activation anneal were performed before the metallization to form n-InGaAs/ p-InGaAs junction. The n-MOSFETs with Si-doped S/D and NiInGaAs contact show significantly suppressed off-state current I OFF as compared with n-MOSFETs with metallic Ni-InGaAs S/D. Device FabricationThe fabrication process flow for In 0.7 Ga 0.3 As channel n-MOSFETs with self-aligned Ni-InGaAs contacts is summarized and illustrated in Fig. 1. 2-in. p-type (N A $1 Â 10 19 cm À3 ) InP wafer was used as starting substrates. A 500 nm thick In 0.53 Ga 0.47 As with p-type (Zn doped) doping concentration N A of 2 Â 10 17 cm À3 and a 20 nm thick In 0.7 Ga 0.3 As with N A of 2 Â 10 16 cm À3 were sequentially grown. After pregate cleaning using HCl and NH 4 OH solution, (NH 4 ) 2 S solution was used to passivate the In 03.7 Ga 0.3 As surface for suppression of surface oxidation. The sample was then quickly loaded into an atomic layer deposition (ALD) tool and $7 nm of Al 2 O 3 was deposited. TaN gate electrode (100 nm thick) was deposited by sputtering, patterned by optical lithography and etched by Cl 2 -based plasma.After gate stack formation, one batch of devices (implanted devices) w...

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“…InGaAs directly grown on Si with a thick buffer layer was reported earlier and found to have excellent metrics in blanket films and for devices such as FinFETs or heterojunction bipolar a N. Daix transistors (HBTs). 9,10 However, due to the large lattice parameter mismatch between Si and InGaAs (approximately 8%), the surface roughness of the as-grown InGaAs is in the range of few nanometers RMS, and it is not compatible with the DWB process (roughness must be less than 0.6-0.7 nm RMS). We smoothed the InGaAs surface down to sub-nanometric RMS roughness by using the chemicalmechanical-polishing (CMP) technique without affecting the structural quality of the layer.…”

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confidence: 99%

Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

et al. 2014

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We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

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Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

Cited by 45 publications

References 4 publications

High transconductance self-aligned gate-last surface channel In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFET

High transconductance self-aligned gate-last surface channel In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFET

Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization

Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

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