Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization

Abstract

In 0.7 Ga 0.3 As channel n-MOSFETs (metal-oxide-semiconductor field-effect transistors) with Si-doped S/D and self-aligned NiInGaAs contact were demonstrated for the first time. The salicide-like metallization process employed a direct reaction between Ni and Si-doped InGaAs, followed by the removal of the unreacted Ni. As compared with n-MOSFETs with metallic Ni-InGaAs S/D (i.e. no Si doping in S/D), n-MOSFETs with Ni-InGaAs contact formed on Si-doped S/D show significantly improved OFFstate current I OFF in the linear and saturation regions.III-V materials such as Indium Gallium Arsenide (InGaAs) and Indium Arsenide (InAs) have significantly higher electron mobility than Silicon (Si) and are attractive for future high speed low power logic applications. 1-12 High performance III-V MOSFETs require low source and drain (S/D) series resistance R S/D , which includes metal-semiconductor contact resistance. 13-18 To achieve low R S/D in III-V FETs, S/D engineering such as selective growth of in situ doped S/D materials 19-21 and self-aligned contacts have been employed. [17][18]21,22 Metallic S/D is another attractive option 23-26 and should preferably be self-aligned to the gate stack. InGaAs channel n-MOSFETs with self-aligned metallic Ni-InGaAs S/D have been demonstrated recently. 25,26 However, the n-MOSFETs with metallic S/D suffer from high leakage current at metal/semiconductor junctions in S/D regions, leading to high drain to source and drain to body leakage current. Low drain junction leakage is needed to achieve low standby power consumption.In this work, In 0.7 Ga 0.3 As channel n-MOSFETs with Si-doped S/ D and self-aligned Ni-InGaAs contact were demonstrated for the first time. The spacer-less metallization process is similar to salicidation and drives the diffusion of Ni into InGaAs for reaction to form a conductive material. S/D implant (Si) and dopant activation anneal were performed before the metallization to form n-InGaAs/ p-InGaAs junction. The n-MOSFETs with Si-doped S/D and NiInGaAs contact show significantly suppressed off-state current I OFF as compared with n-MOSFETs with metallic Ni-InGaAs S/D. Device FabricationThe fabrication process flow for In 0.7 Ga 0.3 As channel n-MOSFETs with self-aligned Ni-InGaAs contacts is summarized and illustrated in Fig. 1. 2-in. p-type (N A $1 Â 10 19 cm À3 ) InP wafer was used as starting substrates. A 500 nm thick In 0.53 Ga 0.47 As with p-type (Zn doped) doping concentration N A of 2 Â 10 17 cm À3 and a 20 nm thick In 0.7 Ga 0.3 As with N A of 2 Â 10 16 cm À3 were sequentially grown. After pregate cleaning using HCl and NH 4 OH solution, (NH 4 ) 2 S solution was used to passivate the In 03.7 Ga 0.3 As surface for suppression of surface oxidation. The sample was then quickly loaded into an atomic layer deposition (ALD) tool and $7 nm of Al 2 O 3 was deposited. TaN gate electrode (100 nm thick) was deposited by sputtering, patterned by optical lithography and etched by Cl 2 -based plasma.After gate stack formation, one batch of devices (implanted devices) w...

Formation of Ultra-thin and Uniform Ni-InGaAs Alloyed Contact for Scaled Metal S/D InGaAs MOSFETs

“…R □ drastically decreases after RTA and the values as low as 25 /□ are obtained even in the samples with t Ni-InGaAs = 6 nm (t Ni = 4 nm, T a < 250˚C). This value is low enough for scaled metal S/D devices and almost the same as that of previous reports [3,4] in spite of the fact that t Ni-InGaAs in this study is much thinner. From these results, it can be confirmed that thin Ni-InGaAs alloyed layers with low R □ , which meets the requirement of scaled metal S/D MOSFETs, are formed through the control of t Ni and T a .…”

“…One of the critical challenges in InGaAs MOSFETs is a formation of low resistance S/D contacts by a self-aligned manner. Recently, a SALICIDE-like contact technology using Ni-InGaAs alloy has been proposed and metal S/D InGaAs nMOSFETs with very low Schottky barrier height have been demonstrated [3,4]. However, thickness controllability and thermal stability of those alloyed layers have not been well investigated yet.…”

Crystal structure and epitaxial relationship of Ni4InGaAs2 films formed on InGaAs by annealing

“…[10][11][12][13] Ni has been used as a contact metal for InGaAs MOSFETs in early work. [20][21][22][23] Ni-InGaAs, which forms an Ohmic contact on n-type InGaAs, can be obtained by a direct reaction between deposited Ni and InGaAs. The presence of Ni at the contact interface with InGaAs improves adhesion between the gold-based alloy and InGaAs, and also promotes interaction between them during metallization.…”

“…[14][15][16] It has been employed in Au-Ge and Au-Sn metallization for forming nonself aligned Ohmic contacts on n-InGaAs or in Au-Zn metallization for forming Ohmic contacts on p-InGaAs. 22,24 Although the metallurgy of the reaction between Ni and GaAs has been extensively reported, [25][26][27] there is a lack of studies on the specifics of Ni reaction with InGaAs to form Ni-InGaAs. [17][18][19] More recently, Ni-InGaAs has been proposed as a candidate for self-aligned contact material for InGaAs.…”

Physical characterization of sub‐32‐nm semiconductor materials and processes using advanced ion beam–based analytical techniques

“…were the first to report on a self‐aligned ohmic contact metal process for III–V MOSFET on the basis of the epitaxial growth of GeSi on n + GaAs and subsequent Ni deposition, forming a low‐resistivity germano‐silicide (NiGeSi) with good morphology . The use of InGaAs as the III–V channel material facilitates a more simplified metallization scheme on the basis of Ni deposition, which can be readily annealed at low temperature to form a low‐resistivity self‐aligned Ni‐InGaAs quaternary alloy …”