Self-aligned double patterning decomposition for overlay minimization and hot spot detection

Zhang, Hongbo; Du, Yuelin; Wong, D.F.; Topaloglu, Rasit Onur

doi:10.1145/2024724.2024741

Cited by 37 publications

(19 citation statements)

References 13 publications

(12 reference statements)

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“…Performing SADP layout decomposition by formulating it into a Boolean satisfactory (SAT) problem was proposed recently [7][8][9]. In HTDP layout decomposition/synthesis, different spacer related design rules and an extra periphery mask not only enable more aggressive density multiplication, but also widen the ranges of both line and space CD and offer quasi-2D design flexibility.…”

Section: Formulation Of Layout Decomposition/synthesis Into a Booleanmentioning

confidence: 99%

<title>Overlay, decomposition and synthesis methodology for hybrid self-aligned triple and negative-tone double patterning</title>

Kang

Chen

2012

Design for Manufacturability Through Design-Process Integration VI

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A hybrid self-aligned triple and negative-tone double patterning (HTDP) technique is proposed to achieve improved resolution and quasi-2D IC design flexibility at lower cost. Critical challenges of HTDP process and its key design issues such as overlay, layout decomposition and synthesis are investigated, and possible design solutions are discussed. It is shown that using mandrel (including assisting mandrel) and spacer engineering, HTDP on-grid layout design is a promising approach to break the limitation of 1-D gridded design. Efficient formulation of HTDP layout decomposition/synthesis into a Boolean satisfactory problem is demonstrated. Moreover, by considering geometric constraints of HTDP layout and several process related assumptions, it is possible to significantly reduce the number of layout features and Boolean input variables. Several examples of 2-D layout are used to demonstrate the process of HTDP decomposition/synthesis, as well as the simplification of its algorithm to reduce runtime. Specifically, preliminary results from implementation of a 2-mask HTDP design for patterning a 2-D dense line/space array with pads are reported.Keywords: hybrid self-aligned triple and negative-tone double patterning (HTDP), self-aligned triple patterning (SATP), negative-tone self-aligned double patterning (nSADP), on-grid design, Boolean satisfactory problem (SAT).

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Section: Formulation Of Layout Decomposition/synthesis Into a Booleanmentioning

confidence: 99%

<title>Overlay, decomposition and synthesis methodology for hybrid self-aligned triple and negative-tone double patterning</title>

Kang

Chen

2012

Design for Manufacturability Through Design-Process Integration VI

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“…Many works have been done to study the decomposition for SID process. [1][2][3][4] However, lacking a proper verification model, all the previous works have a common assumption that the printing contour of the mandrel/trim mask and the spacer shape are rectilinear, and the decomposition results are merely verified by Boolean operations on rectilinear polygons. In fact, even with perfect optical proximity correction (OPC) for the mandrel mask, the spacer shape still gets rounded at convex mandrel corners due to uniform deposition.…”

Section: Introductionmentioning

confidence: 99%

Enhanced spacer-is-dielectric (sid) decomposition flow with model-based verification

Song

Shiely

et al. 2013

SPIE Proceedings

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Self-aligned double patterning (SADP) lithography is a leading candidate for 14nm node lower-metal layer fabrication. Besides the intrinsic overlay-tolerance capability, the accurate spacer width and uniformity control enables such technology to fabricate very narrow and dense patterns. Spacer-is-dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. In the SID process, due to uniform spacer deposition, the spacer shape gets rounded at convex mandrel corners, and disregarding the corner rounding issue during SID decomposition may result in severe residue artifacts on device patterns. Previously, SADP decomposition was merely verified by Boolean operations on the decomposed layers, where the residue artifacts are not even identifiable. This paper proposes a model-based verification method for SID decomposition to identify the artifacts caused by spacer corner rounding. Then targeting residue artifact removal, an enhanced SID decomposition flow is introduced. Simulation results show that residue artifacts are removed effectively through the enhanced SID decomposition strategy.

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“…[3][4][5][6][7][8] However, it is difficult to decide which patterns to select as mandrel and decide where to place trim patterns. To our best knowledge, there is no method to decompose a given layout for SAQP and N times sidewall processes.…”

Section: Introductionmentioning

confidence: 99%

<title>Self-aligned double and quadruple patterning layout principle</title>

Nakayama

Kodama

Kotani

et al. 2012

Design for Manufacturability Through Design-Process Integration VI

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Self-Aligned Double Patterning (SADP) has become one of the most promising processes for 20nm node technology and beyond. Despite its robustness against overlay, it is a challenging process for designers since predicting the wafer image instantly is almost impossible. Self-Aligned Quadruple Patterning (SAQP) is also critical technology for sub-10nm process but more complex than SADP, so it is too difficult to design a layout intuitively. Needless to say designing layout by applying N times sidewalls intuitively is impossible for almost everyone. In this paper, we clarify a new intuitive principle for SADP layout. The principle uses "Base patterns" painted in different two colors interchangeably. The proposed method enables us to design SADP layout simply by connecting and cutting fundamental pattern arbitrarily with a few restrictions. Another benefit is that either of two colors in the pattern can be used as mandrel. We can apply the principle to not only SAQP but also N times sidewall processes. Considering these advantages, layout formed by sidewall process becomes designer-friendly.

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Self-aligned double patterning decomposition for overlay minimization and hot spot detection

Cited by 37 publications

References 13 publications

<title>Overlay, decomposition and synthesis methodology for hybrid self-aligned triple and negative-tone double patterning</title>

<title>Overlay, decomposition and synthesis methodology for hybrid self-aligned triple and negative-tone double patterning</title>

Enhanced spacer-is-dielectric (sid) decomposition flow with model-based verification

<title>Self-aligned double and quadruple patterning layout principle</title>

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