<title>Overlay, decomposition and synthesis methodology for hybrid self-aligned triple and negative-tone double patterning</title>

Abstract

A hybrid self-aligned triple and negative-tone double patterning (HTDP) technique is proposed to achieve improved resolution and quasi-2D IC design flexibility at lower cost. Critical challenges of HTDP process and its key design issues such as overlay, layout decomposition and synthesis are investigated, and possible design solutions are discussed. It is shown that using mandrel (including assisting mandrel) and spacer engineering, HTDP on-grid layout design is a promising approach to break the limitation of 1-D gridded design. Efficient formulation of HTDP layout decomposition/synthesis into a Boolean satisfactory problem is demonstrated. Moreover, by considering geometric constraints of HTDP layout and several process related assumptions, it is possible to significantly reduce the number of layout features and Boolean input variables. Several examples of 2-D layout are used to demonstrate the process of HTDP decomposition/synthesis, as well as the simplification of its algorithm to reduce runtime. Specifically, preliminary results from implementation of a 2-mask HTDP design for patterning a 2-D dense line/space array with pads are reported.Keywords: hybrid self-aligned triple and negative-tone double patterning (HTDP), self-aligned triple patterning (SATP), negative-tone self-aligned double patterning (nSADP), on-grid design, Boolean satisfactory problem (SAT).

Mandrel and spacer engineering based self-aligned triple patterning

“…Apparently, its final features are separately defined by mandrels (via optical lithography) and spacers, which allows 2-D patterns to be included on the mandrel mask. Moreover, a negative tone self-aligned double patterning process can be accommodated into the same flow to create a hybrid patterning (HTDP [7]) technique, as shown in Fig. 1.…”

“…Self-aligned triple patterning (SATP) process, when combined with 193nm immersion lithography, can potentially increase the density of integrated circuits to sub-15nm half pitch [1][2][3]. There has been an emerging interest in cooptimization of SATP and negative tone self-aligned double patterning (nSADP) techniques to open the door to mandrel and spacer engineering for deep nanoscale IC design [7]. By adding only one extra spacer step, SATP process gains 50% improvement in spatial frequency compared with a SADP process.…”

Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniques

“…A common technical roadblock for SAMP/DSA layout decomposition is the lack of mature EDA systems to support their full-chip implementation. Current SAQP processes are mainly for 1-D patterning even several research groups made attempts to extend them to random 2-D patterning [26][27][28][29][30][31]. For instance, the negative-tone SAQP process in which the final spacers are reversed to trenches has been studied for backend M1 patterning [27][28][29].…”

“…SAMP layout decomposition [24][25][26][27][28][29][30][31] needs to deal with the complicated interaction between mandrels and spacers, and possibly extra mask(s) to introduce more 2-D design freedom. Consequently, SAMP layout decomposition is not as intuitive as optical multiple patterning.…”

“…DSA is a cost-effective frequency multiplication process using pre-patterned templates, which is similar to self-aligned multiple patterning (SAMP [18][19][20][21][22][23][24][25][26][27][28][29][30][31]) based on mandrel and spacer engineering. SAMP technique is a proven solution to pattern 1-D structures of both memory and logic devices.…”