2011
DOI: 10.1149/1.3571248
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Selective Area Growth of InP and Defect Elimination on Si (001) Substrates

Abstract: We report the selective area growth of InP layers in submicron trenches on Si (001) substrates by using a thin Ge buffer layer. The antiphase domain boundaries in InP layers are suppressed by engineering the local Ge surface profile. The mechanism of atomic step formation and the corresponding method for step density control are presented. We discuss the impact of the surface profile of the Ge buffer layer on the formation of antiphase domain boundaries as well as on InP nucleation. A minimum step density of 0… Show more

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Cited by 30 publications
(48 citation statements)
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“…Remarkable progress by IMEC in Belgium in the direct selective area growth of III-V compounds on silicon has recently allowed the growth of high-quality InP in narrow SiO 2 trenches on silicon (001) substrates by MOCVD [99]. Wang et al analyzed the lasing performances of a microlaser design similar to that proposed by Larrue et al [52], where an InGaAs/InP pillar was embedded in a silicon PhC cavity [100,101].…”
Section: (D) External Cavity Engineeringmentioning
confidence: 99%
“…Remarkable progress by IMEC in Belgium in the direct selective area growth of III-V compounds on silicon has recently allowed the growth of high-quality InP in narrow SiO 2 trenches on silicon (001) substrates by MOCVD [99]. Wang et al analyzed the lasing performances of a microlaser design similar to that proposed by Larrue et al [52], where an InGaAs/InP pillar was embedded in a silicon PhC cavity [100,101].…”
Section: (D) External Cavity Engineeringmentioning
confidence: 99%
“…[3][4][5] The best option for the growth of such a complex ternary compound would be to make use of InP binary compounds as a buffer for the lattice matched In 0.53 Ga 0.47 As channel. [6][7][8] Nevertheless, for the integration of III-V compounds on Si substrates, many issues still need to be overcome such as the lattice mismatch (f InP/Si ¼ 8.06%) as well as the polar/non-polar interfaces resulting in the generation of crystalline defects in high density: misfit and threading dislocations, twins, stacking faults, anti-phase boundaries, which would strongly degrade the device performances. Several options have been considered to obtain high quality single crystal III-V compounds on Si with low defect density: strain relaxed buffers, 9,10 epitaxial lateral overgrowth, 11 rapid melt growth, 12 and the defect confinement technique.…”
mentioning
confidence: 99%
“…On Si(001) substrate Chin et al fabricated Si 0. 35 Ge 0.65 -on-SiO 2 structures by deposition of a Si 0.85 Ge 0.15 layer onto a SOI substrate and subsequent two-step Ge condensation process [23]. After photolithography and dry etching lateral Si 0.…”
Section: Theoretical Descriptionmentioning
confidence: 99%
“…After photolithography and dry etching lateral Si 0. 35 Ge 0.65 nanowires on SiO 2 were obtained, which served for the study of selective migration enhanced epitaxy (MEE) growth of GaAs onto the nanowires (Figure 7). Owing to the pulsed Ga and As fluxes and intermittent annealing phases in MEE, selective growth is achieved even in the case of masks patterned on the micrometre scale.…”
Section: Theoretical Descriptionmentioning
confidence: 99%
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