SEGR study on Power MOSFETs: Multiple impacts assumption

Abstract

The main em phasis of this study is the investigation of the gate degradation or rupture, aiming to determine the nature of the so-called SEGR phenomena. This article presents experimental data showing heavy ions induced gate degradation in power MOSFETs. In the experiments, backside and front-side irradiations are performed. The heavy ions ranges are tuned in such way to control whether they hit the gate or not, during backside irradiation. Gate-to-source current Igss (4)) is measured versus Heavy Ions (H.I.) fluence 4>. Post-irradiation-Gate-StressTest (PGST) allows to measure breakdown voltage VBD(4)) as being decreasing with (H.I.) fluence. Based on these experimental results, an hypothesis of substrate-generated "hot carriers" impact overlap may explain gate degradation until SEGR triggering. This last hypothesis is supported by statistical approach model of heavy ions multiple impact.

Effects of Ion Atomic Number on Single-Event Gate Rupture (SEGR) Susceptibility of Power MOSFETs

“…For each sample, the gate-source bias was held at -10 V to assure that SEGR would occur during exposure to lighter, lower-LET ions. At this bias, effects of multiple proximal ion impacts are reduced [4,5], making the data easier to interpret. Vds was incremented in 5-volt steps; at each step, the sample was irradiated until either the sample failed or a fluence of 3x105 ions/cm 2 was reached.…”

On the Use of Post-Irradiation-Gate-Stress Results to Refine Sensitive Operating Area Determination

“…Irradiations were performed at normal incidence (i.e., at an angle of with respect to the device's surface) with an average flux about ions cm . Use of a lower flux reduces the likelihood of multiple impact effects [17]. Heavy-ion irradiation was stopped when either a destructive event occurs or a fluence of ions cm is reached.…”