An Updated Perspective of Single Event Gate Rupture and Single Event Burnout in Power MOSFETs

A Brief Review of Heavy-Ion Radiation Degradation and Failure of Silicon UMOS Power Transistors

“…Simulations indicated that enlarging the p + plug and the addition of a buffer layer between the epitaxial layer and substrate can reduce SEB susceptibility with the buffer layer making the most difference. These results are similar to results obtained for VDMOS devices [19]. Using TCAD simulation, Wang et al [23] have also been able to explore the potential for hardening using alternate structural configurations such as including a Schottky source plus an N-type buffer layer.…”

“…Additionally, with evidence that device bias voltages at which SEB and SEGR occurs in VDMOS (or the determination of a device's safe operating area) may be linked to the ion energy and ion species [19,29,30] rather than linked solely to the LET of the ion, worst-case conditions for radiation hardness assurance testing and qualification of UMOS power transistors for use in space should be carefully examined.…”

“…Koga et al [9], in a 2014 paper, note similar results. A recent review paper by Titus [19] describes test circuits and methodology for such tests. During exposure to heavy ion radiation, the drain leakage current will suddenly increase to the allowed current limit while the gate leakage current remains at the base level.…”

Single-Event Burnout Hardened Structure of Power UMOSFETs With Schottky Source

“…Then, the effects of ion species [13] and the sensitive volume for SEB performance of power MOSFETs have been discussed in detail [14], [15]. The research and exploration of SEB in power MOSFETs have been continued in recent years [16], [17], and 2-D simulators are used to investigate SEB performance [18], [19].The time evolution of SEB and the evaluation on protective SEB test method of power MOSFET have also been discussed [20], [21]. Many hardening solutions to SEB of power DMOSFETs have been extensively investigated and tested these years.…”

Charge Collection Mechanisms in AlGaN/GaN MOS High Electron Mobility Transistors

“…The mechanisms of single-event gate rupture (SEGR) are not completely understood [49]; hole pile-up near the interface, however, plays a role by increasing the electric field in the gate oxide. [26].…”