SDA: Software-defined accelerator for large-scale DNN systems

Ouyang, Jian; Lin, Shiding; Wei, Qi; Wang, Yong; Yu, Bo; Jiang, Song

doi:10.1109/hotchips.2014.7478821

Cited by 65 publications

(48 citation statements)

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“…This is shown, e.g. by the decision by Baidu to accelerate its deep learning models for image search by using FPGAs [3]. Similarly, Microsoft, after years of research to accelerate its Bing search engine, is now also looking into how to accelerate deep learning models through FPGAs [4].…”

Section: B Overview Of Openclmentioning

confidence: 99%

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Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL

Muslim

Demian²,

et al. 2016

Annals of Computer Science and Information Systems

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Abstract-ModernSoCs are getting increasingly heterogeneous with a combination of multi-core architectures and hardware accelerators to speed up the execution of computeintensive tasks at considerably lower power consumption. Modern FPGAs, due to their reasonable execution speed and comparatively lower power consumption, are strong competitors to the traditional GPU based accelerators. High-level Synthesis (HLS) simplifies FPGA programming by allowing designers to program FPGAs in several high-level languages e.g. C/C++, OpenCL and SystemC.This work focuses on using an HLS based methodology to implement a widely used classification algorithm i.e. k-nearest neighbor on an FPGA based platform directly from its OpenCL code. Multiple fairly different implementations of the algorithm are considered and their performance on FPGA and GPU is compared. It is concluded that the FPGA generally proves to be more power efficient as compared to the GPU. Furthermore, using an FPGA-specific OpenCL coding style and providing appropriate HLS directives can yield an FPGA implementation comparable to a GPU also in terms of execution time.

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Section: B Overview Of Openclmentioning

confidence: 99%

“…Modern FPGAs have the ability to provide sufficient processing speed while consuming a fraction of the power consumed by high-end GPUs [2]. This is why several big data companies such as Microsoft, Baidu are exploring FPGA devices as accelerators rather than GPUs [3,4].…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL

Muslim

Demian²,

et al. 2016

Annals of Computer Science and Information Systems

View full text Add to dashboard Cite

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“…They report almost doubled throughput in search ranking at a cost of only 10% increased power consumption and 30% increased total cost of ownership. Baidu presented accelerated neural networks on FPGAs in the datacenter offering an order of magnitude better performance at minimal additional power cost [13]. In [14], the authors present FPGAs in the cloud as standalone resources, treated separately from standard (server) resources.…”

Section: Existing Workmentioning

confidence: 99%

Virtualized FPGA Accelerators for Efficient Cloud Computing

Fahmy

Vipin

Shreejith

2015

2015 IEEE 7th International Conference on Cloud Computing Technology and Science (CloudCom)

127

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“…However, using such an index does not remove all the file system overhead from the IO-path. It is well known that permission checks of file systems increase latency in the IOpath by 10-15µs [13,43]. A combined memory and storagelevel indirection layer would not only eliminate a level of indirection but would also perform all the necessary checks efficiently by using the protection bits in the page tables.…”

Section: Challenges For a Combined Indirection Layermentioning

confidence: 99%

Unified address translation for memory-mapped SSDs with FlashMap

Huang

Badam

Qureshi

et al. 2015

SIGARCH Comput. Archit. News

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Applications can map data on SSDs into virtual memory to transparently scale beyond DRAM capacity, permitting them to leverage high SSD capacities with few code changes. Obtaining good performance for memory-mapped SSD content, however, is hard because the virtual memory layer, the file system and the flash translation layer (FTL) perform address translations, sanity and permission checks independently from each other. We introduce FlashMap, an SSD interface that is optimized for memory-mapped SSD-files. FlashMap combines all the address translations into page tables that are used to index files and also to store the FTL-level mappings without altering the guarantees of the file system or the FTL. It uses the state in the OS memory manager and the page tables to perform sanity and permission checks respectively. By combining these layers, FlashMap reduces critical-path latency and improves DRAM caching efficiency. We find that this increases performance for applications by up to 3.32x compared to state-of-the-art SSD file-mapping mechanisms. Additionally, latency of SSD accesses reduces by up to 53.2%.

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SDA: Software-defined accelerator for large-scale DNN systems

Cited by 65 publications

References 0 publications

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL

Virtualized FPGA Accelerators for Efficient Cloud Computing

Unified address translation for memory-mapped SSDs with FlashMap

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