Emerging byte-addressable, non-volatile memory technologies (NVRAM) like phase-change memory can increase the capacity of future memory systems by orders of magnitude. Compared to systems that rely on disk storage, NVRAMbased systems promise significant improvements in performance for key applications like online transaction processing (OLTP). Unfortunately, NVRAM systems suffer from two drawbacks: their asymmetric read-write performance and the notable higher cost of the new memory technologies compared to disk. This paper investigates the cost-effective use of NVRAM in transaction systems. It shows that using NVRAM only for the logging subsystem (NV-Logging) provides much higher transactions per dollar than simply replacing all disk storage with NVRAM. Specifically, for NV-Logging, we show that the software overheads associated with centralized log buffers cause performance bottlenecks and limit scaling. The per-transaction logging methods described in the paper help avoid these overheads, enabling concurrent logging for multiple transactions. Experimental results with a faithful emulation of future NVRAM-based servers using the TPCC, TATP, and TPCB benchmarks show that NV-Logging improves throughput by 1.42 -2.72x over the costlier option of replacing all disk storage with NVRAM. Results also show that NV-Logging performs 1.21 -6.71x better than when logs are placed into the PMFS NVRAM-optimized file system. Compared to state-of-theart distributed logging, NV-Logging delivers 20.4% throughput improvements.

Traditional human emotion recognition is based on electroencephalogram (EEG) data collection technologies which rely on plenty of rigid electrodes and lack anti‐interference, wearing comfort, and portability. Moreover, a significant distribution difference in EEG data also results in low classification accuracy. Here, on‐skin biosensors with adhesive and hydrophobic bilayer hydrogel (AHBH) as interfaces for high accuracy emotion classification are proposed. The AHBH achieves remarkable adhesion (59.7 N m−1) by combining the adhesion mechanism of catechol groups and electrostatic attraction. Meanwhile, based on the synergistic effects of hydrophobic group rearrangements and surface energy reduction, the AHB‐hydrophobic layer exhibits 133.87° water contact angles through hydrophobic treatment of only 0.5 h. Hydrogen and electrostatic bonds are also introduced to form a seamless adhesive‐hydrophobic hydrogel interface and inhibit adhesion attenuation, respectively. With the AHBH as an ideal device/skin interface, the biosensor can reliably collect high‐quality electrophysiological signals even under vibration, sweating, and long‐lasting monitoring condition. Furthermore, the on‐skin electrodes, data processing, and wireless modules are integrated into a portable headband for EEG‐based emotion classification. A domain adaptive neural network based on the transfer learning technique is introduced to alleviate the effect of domain shift and achieve high classification accuracy.

No abstract

No abstract

Speculative execution and instruction reuse are two important strategies that have been investigated for improving processor performance. Value prediction at the instruction level has been introduced to allow even more aggressive speculation and reuse than previous techniques. This study suggests that using compiler support to extend value reuse to a coarser granularity than a single instruction, such as a basic block, may have substantial performance benefits. We investigate the input and output values of basic blocks and find that these values can be quite regular and predictable. For the SPEC benchmark programs evaluated, 90% of the basic blocks have fewer than 4 register inputs, 5 live register outputs, 4 memory inputs and 2 memory outputs. About 16% to 41% of all the basic blocks are simply repeating earlier calculations when the programs are compiled with the-O2 optimization level in the GCC compiler. Compiler optimizations, such as loop-unrolling and function inlining, affect the sizes of basic blocks, but have no significant or consistent impact on their value locality, nor the resulting performance. Based on these results, we evaluate the potential benefit of basic block reuse using a novel mechanism called the block history buffer. This mechanism records input and live output values of basic blocks to provide value reuse at the basic block level. Simulation results show that using a reasonably-sized block history buffer to provide basic block reuse in a 4-way issue superscalar processor can improve execution time for the tested SPEC programs by 1% to 14% with an overall average of 9% when using reasonable hardware assumptions.

No abstract

No abstract

No abstract